IP Library Granted Patent US 11,824,525
Granted Patent B2
US 11,824,525 · App. 17/498,101 · Granted Nov 21, 2023

T-switch with reduced current leakage

Inventor: Ajay Kumar (Phoenix, AZ)
Assignee: Microchip Technology Incorporated
H03K17/16H03M1/12
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Quick Facts
Patent No.
US 11,824,525
App. No.
17/498,101
Granted
Nov 21, 2023
Kind
B2
Abstract

An apparatus is provided comprising a first t-switch, which includes an input port arranged to be connected to a first voltage source, a center-tap port, and an output port arranged to be connected to a load. The first t-switch is configured to connect the input port to the output port in an on mode and disconnect the input port from the output port in an off mode. The apparatus further comprises a bias voltage generation circuit configured to generate a bias voltage, the generated bias voltage coupled to the center-tap port of the first t-switch, the bias voltage determined based upon an output port voltage.

Claims (57)

1. An apparatus, comprising:

a first t-switch, including:

an input port arranged to be connected to a first voltage source;

a center-tap port; and

an output port arranged to be connected to a load;

wherein the first t-switch is to:

connect the input port to the output port in an on mode; and

disconnect the input port from the output port in an off mode; and

a bias voltage generation circuit (BVGC) having an input coupled to the output port of the first t-switch to generate a bias voltage, the generated bias voltage coupled to the center-tap port of the first t-switch, the bias voltage determined based upon a voltage of the output port, and wherein the bias voltage is determined independent of any voltage downstream of the output port.

2. The apparatus of claim 1 , wherein the BVGC is to buffer the output port voltage to generate the bias voltage.

3. The apparatus of claim 1 , wherein the BVGC is to add an offset voltage to the output port voltage to generate the bias voltage.

4. The apparatus of claim 1 , further comprising a control logic, the control logic to, in the off mode, cause the first t-switch to connect the bias voltage on the center-tap port to a midpoint between the input port and the output port of the first t-switch.

5. The apparatus of claim 1 , further comprising a control logic, the control logic to, in the on mode, cause the first t-switch to disconnect the bias voltage on the center-tap port from a midpoint between the input port and from the output port of the first t-switch.

6. The apparatus of claim 1 , wherein the bias voltage is to reduce a voltage differential between the output port and the center-tap port in both the on mode and the off mode of the first t-switch as compared to application of a ground voltage to the center-tap port.

7. The apparatus of claim 1 , wherein application of the bias voltage to the center-tap port of the first t-switch is to reduce a current leak from the output port to the center-tap port of the first t-switch as compared to application of a ground voltage to the center-tap port.

8. The apparatus of claim 1 , wherein the BVGC is implemented with an operational amplifier with a first input connected to the output port voltage and a second input connected to feedback from an output of the operational amplifier.

9. The apparatus of claim 1 , wherein the first t-switch is implemented by a first sub-switch connected between the input port and a midpoint, a second sub-switch connected between the midpoint and the output port, and a third sub-switch connected between the midpoint and the center-tap port.

10. The apparatus of claim 9 , wherein the first t-switch is to, in the on mode:

close the first sub-switch;

close the second sub-switch; and

open the third sub-switch.

11. The apparatus of claim 9 , wherein the first t-switch is to, in the off mode:

open the first sub-switch;

open the second sub-switch; and

close the third sub-switch.

12. The apparatus of claim 1 , further comprising:

a plurality of second t-switches, wherein:

each second t-switch includes:

an input port to be connected to a respective second voltage source;

a center-tap port coupled to the generated bias voltage; and

an output port to be connected to the load; and

each second t-switch is to:

connect the input port to the output port of the second t-switch in an on mode; and

disconnect the input port from the output port of the second t-switch in an off mode; and

control logic to:

select one of the first t-switch and the second t-switches;

set the selected one of the first t-switch and the second t-switches to the on mode; and

set all remaining ones of the first t-switch and the second t-switches to the off mode.

13. The apparatus of claim 12 , wherein the load is an analog to digital converter (ADC) including a sample and hold capacitor, the sample and hold capacitor to be reused with a digital to analog converter (DAC).

14. The apparatus of claim 12 , wherein:

the load is an analog to digital converter (ADC);

the first t-switch and the plurality of second t-switches form an N:1 ADC input channel for the ADC, wherein N is greater than two; and

the control logic is to:

determine a selected voltage source from the first voltage source and the second voltage sources, the selected voltage source to be converted by the ADC and be set as the sampled voltage; and

cause the N:1 ADC input channel to route the selected voltage source of the first voltage source and the second voltages sources to the ADC.

15. A method for controlling a first t-switch comprising an input port arranged to be connected to a first voltage source, a center-tap port, and an output port arranged to be connected to a load, the method comprising:

connecting the input port to the output port in an on mode;

disconnecting the input port from the output port in an off mode; and

generating a bias voltage coupled to the center-tap port of the first t-switch, wherein the bias voltage determined based upon a voltage of the output port, and wherein the bias voltage is determined independent of any voltage downstream of the output port.

16. The method of claim 15 further comprising buffering the output port voltage to generate the bias voltage.

17. The method of claim 15 further comprising adding an offset voltage to the output port voltage to generate the bias voltage.

18. The method of claim 15 further comprising, in the off mode, causing the first t-switch to connect the bias voltage on the center-tap port to a midpoint between the input port and the output port of the first t-switch.

19. The method of claim 15 , further comprising, in the on mode, causing the first t-switch to disconnect the bias voltage on the center-tap port from a midpoint between the input port and from the output port of the first t-switch.

20. The method of claim 15 , the method for additionally controlling a plurality of second t-switches, wherein each second t-switch includes an input port to be connected to a respective second voltage source, a center-tap port coupled to the generated bias voltage, and an output port to be connected to the load, the method further comprising:

selecting one of the first t-switch and the second t-switches;

setting the selected one of the first t-switch and the second t-switches to the on mode; and

setting all remaining ones of the first t-switch and the second t-switches to the off mode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2021
From: KUMAR, AJAY
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 057772/0222 →