Artificial neuron
An artificial neuron includes a first capacitive node of application of a membrane potential of the neuron. A first transistor is configured to discharge the first capacitive node. A second capacitive node is driven according to the membrane potential and delivers a potential for controlling the first transistor. A second transistor is configured to discharge the second capacitive node. The second transistor is controlled according to a potential present at the second capacitive node.
1 . An electronic circuit of an artificial neuron, comprising:
a first capacitive node of application of a membrane potential of the artificial neuron;
a first transistor for discharging the first capacitive node;
a second capacitive node driven according to the membrane potential and delivering a potential for controlling the first transistor;
a second transistor for discharging the second capacitive node; and
a control circuit configured to activate the second transistor in response to sensing a discharge of the second capacitive node below a threshold;
wherein the second transistor is controlled according to a potential present at the second capacitive node.
2 . The circuit according to claim 1 , wherein the control circuit comprises an inverter having an input connected to the second capacitive node and having an output connected to a gate of the second transistor.
3 . The circuit according to claim 1 , wherein the second capacitive node is coupled to the first capacitive node by first and second inverters coupled in series at a fourth node.
4 . The circuit according to claim 1 , further comprising a fourth transistor coupled to the first capacitive node and to a fifth node of application of a potential for powering the artificial neuron.
5 . An artificial neural network comprising at least one circuit according to claim 1 .
6 . An electronic circuit of an artificial neuron, comprising:
a first capacitive node of application of a membrane potential of the artificial neuron;
a first transistor for discharging the first capacitive node;
a second capacitive node driven according to the membrane potential and delivering a potential for controlling the first transistor;
a second transistor for discharging the second capacitive node,
wherein the second transistor is controlled according to a potential present at the second capacitive node;
wherein the second capacitive node is coupled to the first capacitive node by first and second inverters coupled in series at a fourth node; and
a third transistor connected between a gate of the second transistor and a third node of application of a reference potential, wherein a gate of the third transistor is coupled by a third inverter to the fourth node.
7 . The circuit according to claim 6 , wherein the second capacitive node is coupled to the first capacitive node by first and second inverters coupled in series at a fourth node.
8 . The circuit according to claim 6 , further comprising a fourth transistor coupled to the first capacitive node and to a fifth node of application of a potential for powering the artificial neuron.
9 . The circuit according to claim 6 , further comprising a control circuit configured to activate the second transistor in response to sensing a discharge of the second capacitive node below a threshold.
10 . An artificial neural network comprising at least one circuit according to claim 6 .
11 . An electronic circuit of an artificial neuron, comprising:
a first capacitive node of application of a membrane potential of the artificial neuron;
a first transistor for discharging the first capacitive node;
a second capacitive node driven according to the membrane potential and delivering a potential for controlling the first transistor;
a second transistor for discharging the second capacitive node,
wherein the second transistor is controlled according to a potential present at the second capacitive node; and
a fourth transistor coupled to the first capacitive node and to a fifth node of application of a potential for powering the artificial neuron;
wherein the gate of the fourth transistor is connected to an output of a NOR gate having a first input connected to the gate of the second transistor and a second input connected to the first capacitive node.
12 . The circuit according to claim 11 , wherein the second capacitive node is coupled to the first capacitive node by first and second inverters coupled in series at a fourth node.
13 . The circuit according to claim 11 , further comprising a control circuit configured to activate the second transistor in response to sensing a discharge of the second capacitive node below a threshold.
14 . An artificial neural network comprising at least one circuit according to claim 11 .
15 . An electronic circuit of an artificial neuron, comprising:
a first capacitive node of application of a membrane potential of the artificial neuron;
a first transistor for discharging the first capacitive node;
a second capacitive node driven according to the membrane potential and delivering a potential for controlling the first transistor;
a second transistor for discharging the second capacitive node,
wherein the second transistor is controlled according to a potential present at the second capacitive node; and
a fourth transistor coupled to the first capacitive node and to a fifth node of application of a potential for powering the artificial neuron;
wherein the fourth transistor is coupled to the first capacitive node by a fifth transistor having a gate configured to receive a potential for exciting the artificial neuron.
16 . The circuit according to claim 15 , wherein the second capacitive node is coupled to the first capacitive node by first and second inverters coupled in series at a fourth node.
17 . The circuit according to claim 15 , further comprising a control circuit configured to activate the second transistor in response to sensing a discharge of the second capacitive node below a threshold.
18 . An artificial neural network comprising at least one circuit according to claim 15 .