Three dimensional circuit implementing machine trained network
Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.
1. A circuit comprising:
a first bonded layer; and
a second bonded layer vertically stacked with the first bonded layer;
wherein the first bonded layer comprises at least one processing node adapted for machine-training; and
wherein the second bonded layer comprises one or more memories electrically connected to the at least one processing node and configured to receive one or both of input for or output produced by the at least one processing node.
2. The circuit of claim 1 , wherein the one or more memories comprise a first memory to store the input for the at least one processing node, and a second memory to store the output produced by the at least one processing node.
3. The circuit of claim 1 , wherein the first bonded layer comprises a plurality of processing nodes forming a network adapted for machine-training in which an output of one of the processing nodes serves as an input for another one of the processing nodes.
4. The circuit of claim 3 , wherein the network is a neural network and the processing nodes serve as neurons.
5. The circuit of claim 4 , wherein the neural network comprises multiple stages of neurons with a routing fabric that drives output of earlier stage neurons to input of later stage neurons.
6. The circuit of claim 1 , wherein one of the first and second bonded layers is an integrated circuit (IC) die and the other of the first and second bonded layers is an IC wafer.
7. The circuit of claim 1 , wherein the first and second bonded layers are first and second integrated circuit (IC) dies.
8. The circuit of claim 7 , wherein the first and second IC dies have a same size.
9. The circuit of claim 7 , wherein the first and second IC dies have bounding shapes that overlap each other.
10. The circuit of claim 1 , wherein the first and second bonded layers are first and second integrated circuit (IC) wafers.
11. The circuit of claim 1 , wherein the one or more memories of the second bonded layer are connected to the at least one processing node through a vertical conductive interface.
12. The circuit of claim 11 , wherein the vertical conductive interface comprises through-silicon vias or direct bonded interconnect connections.
13. The circuit of claim 11 , wherein the one or more memories of the second layer includes a plurality of memory arrays and at least two of the memory arrays are connected to the at least one processing node through the vertical conductive interface.
14. The circuit of claim 1 , wherein each of the first and second bonded layers comprises (i) an integrated circuit substrate on which a plurality of circuit components are defined and (ii) a plurality of wiring layers for connecting the circuit components.
15. The circuit of claim 1 , further comprising a third bonded layer comprising a second set of one or more memories.
16. The circuit of claim 15 , wherein the one or more memories of the second bonded layer comprise output memory and the second set of one or more memories of the third bonded layer comprises a parameter memory.
17. The circuit of claim 1 , wherein the one or more memories are electrically connected to the at least one processing node by hybrid bonding.
18. A circuit comprising:
a first layer comprising a network adapted for machine-training; and
a second layer vertically stacked with the first layer, the second layer comprising one or more memories;
wherein the network of the first layer is electrically coupled to the one or more memories of the second layer, and
wherein the one or more memories are configured to receive one or both of input for or output produced by the network.
19. The circuit of claim 18 , wherein the network comprises a plurality of processing nodes.
20. The circuit of claim 19 , wherein the network is a neural network and the processing nodes comprise neurons.
21. The circuit of claim 18 , wherein the one or more memories comprise a first memory to store machine-trained parameters for the network, and a second memory to store values produced by the network.
22. The circuit of claim 18 , wherein the one or more memories are electrically coupled to the network by hybrid bonding.