Scan driver and driving method thereof
A scan driver and a driving method thereof, in which the scan driver includes a plurality of stages outputting an output signal in response to clock signals supplied at a first frequency during a driving time of one frame, wherein the plurality of stages are supplied with the clock signals at a second frequency lower than the first frequency during a hold time of the one frame that is separate from the driving time of the one frame.
1. A scan driver comprising:
a plurality of stages configured to output an output signal in response to clock signals supplied at a first frequency during a driving time of one frame,
wherein the plurality of stages are supplied with the clock signals at a second frequency lower than the first frequency during a hold time of the one frame that is separate from the driving time of the one frame; and
the clock signals include a first clock signal and a second clock signal,
wherein each of the plurality of stages includes:
an input portion controlling a voltage of a first node and a voltage of a second node based on signals supplied to a first input terminal and a second input terminal;
a first signal processing portion that supplies a voltage of a second power source to a fourth node based on the voltage of the first node, or electrically connects the second node and the fourth node through a fifth node based on a voltage of a first power source;
a second signal processing portion that includes a first transistor connected between a third node and a sixth node, and is connected to the first input terminal, the second input terminal, and the first power source to control a voltage of the third node based on an operation of the first transistor; and
an output portion that controls a voltage applied to the third node to be less than or equal to the voltage of the first power source, and supplies the voltage of the first power source or the voltage of the second power source to an output terminal as a scan signal based on the voltage of the third node and a voltage of the fourth node.
2. The scan driver of claim 1 , wherein
the plurality of stages do not output the output signal during the hold time of the one frame, and
the clock signals maintain a constant voltage level during the hold time of the one frame.
3. The scan driver of claim 1 , wherein
the clock signals repeat a low voltage level and a high voltage level more than once during the hold time of the one frame.
4. The scan driver of claim 1 , wherein the output portion includes:
a second transistor that is connected between the second power source and the output terminal, and of which a gate electrode receives the voltage of the fourth node; and
a third transistor that is connected between the output terminal and the first power source, and of which a gate electrode receives the voltage of the third node.
5. The scan driver of claim 4 , wherein
the input portion includes:
a fourth transistor that is connected between the first input terminal and the first node, and of which a gate electrode is connected to the second input terminal to receive the first clock signal;
a fifth transistor that is connected between the second input terminal and the second node, and of which a gate electrode receives the voltage of the first node; and
a sixth transistor that is connected between the second node and the first power source, and of which a gate electrode is connected to the second input terminal to receive the first clock signal.
6. The scan driver of claim 5 , wherein
the first signal processing portion includes:
a second capacitor having a first end connected to the fifth node and a second end connected to a first electrode of an eighth transistor;
a seventh transistor that is connected between the first electrode of the eighth transistor and a third input terminal, and of which a gate electrode receives a voltage of the fifth node;
the eighth transistor that is connected between a first electrode of the seventh transistor and the fourth node, and of which a gate electrode receives the second clock signal supplied from the third input terminal;
a first capacitor having a first end connected to the fourth node and a second end connected to the second power source;
a fourth capacitor having a first end connected to the first node and a second end connected to the second power source;
a ninth transistor that is connected between the fourth node and the second power source, and of which a gate electrode receives the voltage of the first node; and
a tenth transistor that is connected between the first node and the second power source, and of which a gate electrode is connected to a reset input terminal.
7. The scan driver of claim 6 , wherein
the second signal processing portion further includes:
an eleventh transistor that is connected between the first input terminal and a thirteenth transistor, and of which a gate electrode receives the first clock signal supplied from the second input terminal;
the thirteenth transistor that is connected between the eleventh transistor and the sixth node, and of which a gate electrode receives the voltage of the first power source;
a fourteenth transistor that is connected between the third input terminal and a seventh node, and of which a gate electrode receives a voltage of the sixth node;
a third capacitor having a first end connected to the sixth node and a second end connected to the seventh node; and
a fifteenth transistor that is connected between the seventh node and the second power source, and of which a gate electrode receives the voltage of the second node.
8. The scan driver of claim 7 , wherein each of the plurality of stages further includes:
a stabilizing portion that is electrically connected between the input portion and the output portion, and limits a voltage drop amount of the first node and a voltage drop amount of the second node, and
the stabilizing portion includes:
a sixteenth transistor that is connected between the second node and the fifth node, and of which a gate electrode receives the voltage of the first power source;
a seventeenth transistor that is connected between the first node and an eighteenth transistor, and of which a gate electrode receives the first clock signal; and
the eighteenth transistor that is connected between the seventeenth transistor and the third node, and of which a gate electrode receives the voltage of the first power source.
9. The scan driver of claim 1 , wherein each of the plurality of stages further includes:
a fifth capacitor having a first end connected to the third node and a second end connected to the first power source, and
the fifth capacitor stores the voltage of the third node.
10. The scan driver of claim 5 , wherein
the first signal processing portion includes:
a second capacitor having a first end connected to the fifth node and a second end connected to a first electrode of a ninth transistor;
an eighth transistor that is connected between the first electrode of the ninth transistor and a third input terminal, and of which a gate electrode receives a voltage of the fifth node;
the ninth transistor that is connected between a first electrode of the eighth transistor and the fourth node, and of which a gate electrode receives the second clock signal supplied from the third input terminal;
a first capacitor having a first end connected to the fourth node and a second end connected to the second power source;
a tenth transistor that is connected between the fourth node and the second power source, and of which a gate electrode receives the voltage of the first node; and
an eleventh transistor that is connected between the first node and the second power source, and of which a gate electrode is connected to a input terminal.
11. The scan driver of claim 10 , wherein
the second signal processing portion further includes:
a twelfth transistor that is connected between the first input terminal and a fourteenth transistor, and of which a gate electrode receives a first clock signal supplied from the second input terminal;
the fourteenth transistor that is connected between the twelfth transistor and the sixth node, and of which a gate electrode receives the voltage of the first power source;
a fifteenth transistor that is connected between the third input terminal and a seventh node, and of which a gate electrode receives a voltage of the sixth node;
a third capacitor having a first end connected to the sixth node and a second end connected to the seventh node; and
a sixteenth transistor that is connected between the seventh node and the second power source, and of which a gate electrode receives the voltage of the second node.
12. The scan driver of claim 11 , wherein each of the plurality of stages further includes:
a stabilizing portion that is electrically connected between the input portion and the output portion, and limits a voltage drop amount of the first node and a voltage drop amount of the second node.
13. The scan driver of claim 12 , wherein the stabilizing portion includes:
a seventeenth transistor that is connected between the second node and the fifth node, and of which a gate electrode receives the voltage of the first power source; and
an eighteenth transistor that is connected between the first node and the third node, and of which a gate electrode receive the voltage of the first power source.
14. The scan driver of claim 10 , each of the plurality of stages further includes:
a fifth capacitor having a first end connected to the third node and a second end connected to the first power source, and
the fifth capacitor stores the voltage of the third node.
15. A driving method of a scan driver that includes a plurality of stages, comprising:
outputting, by the plurality of stages, a plurality of output signals in response to clock signals supplied at a first frequency during a driving time of one frame; and
receiving, by the plurality of stages, the clock signals at a second frequency lower than the first frequency during a hold time of the one frame that is separate from the driving time of the one frame,
wherein each of the plurality of stages includes:
an input portion controlling a voltage of a first node and a voltage of a second node based on signals supplied to a first input terminal and a second input terminal;
a first signal processing portion that supplies a voltage of a second power source to a fourth node based on the voltage of the first node, or electrically connects the second node and the fourth node through a fifth node based on a voltage of a first power source;
a second signal processing portion that includes a first transistor connected between a third node and a sixth node, and is connected to the first input terminal, the second input terminal, and the first power source to control a voltage of the third node based on an operation of the first transistor; and
an output portion that controls a voltage applied to the third node to be less than or equal to the voltage of the first power source, and supplies the voltage of the first power source or the voltage of the second power source to an output terminal as a scan signal based on the voltage of the third node and a voltage of the fourth node.
16. The driving method of the scan driver of claim 15 ,
wherein
the stages do not output the plurality of output signals during the hold time of the one frame.
17. The driving method of the scan driver of claim 15 , wherein
the clock signals maintain a constant voltage level during the hold time of the one frame.
18. The driving method of the scan driver of claim 15 , wherein
the clock signals repeat a low voltage level and a high voltage level more than once during the hold time of the one frame.