Hardware accelerator
A hardware accelerator is provided. The hardware accelerator includes a first memory; a source address generation unit coupled to the first memory; a data collection unit coupled to the first memory; a first data queue coupled to the data collection unit; a data dispersion unit coupled to the first data queue; a destination address generation unit coupled to the data dispersion unit; an address queue coupled to the destination address generation unit; a second data queue coupled to the data dispersion unit; and a second memory coupled to the second data queue. The hardware accelerator can perform anyone or any combination of tensor stride, tensor reshape and tensor transpose to achieve tensorflow depth-to-space permutation or tensorflow space-to-depth permutation.
1. A hardware accelerator, comprising:
a first memory used for receiving data;
a source address generation unit coupled to the first memory for generating a plurality of source addresses to the first memory according to a source shape parameter and a source stride parameter, wherein the first memory transmits data according to the source addresses;
a data collection unit coupled to the first memory used for receiving data transmitted from the first memory;
a first data queue coupled to the data collection unit used for temporarily storing data transmitted from the data collection unit;
a data dispersion unit coupled to the first data queue used for dispersing data transmitted from the first data queue;
a destination address generation unit coupled to the data dispersion unit for generating a plurality of destination addresses according to a destination shape parameter and a destination stride parameter;
an address queue coupled to the destination address generation unit for temporarily storing the destination addresses generated by the destination address generation unit;
a second data queue coupled to the data dispersion unit for temporarily storing data transmitted from the data dispersion unit; and
a second memory coupled to the second data queue for writing data transmitted from the second data queue according to the destination addresses generated by the destination address generation unit,
wherein the hardware accelerator performs tensor stride, tensor reshape and tensor transpose to achieve tensorflow depth-to-space permutation and tensorflow space-to-depth permutation, and
after tensor stride is performed, the source shape parameter and the destination shape parameter are the same, but the source stride parameter and the destination stride parameter are different.
2. The hardware accelerator according to claim 1 , wherein the source shape parameter and the source stride parameter are user defined parameters.
3. The hardware accelerator according to claim 1 , wherein the destination shape parameter and the destination stride parameter are user defined parameters.
4. The hardware accelerator according to claim 1 , wherein after tensor reshape is performed, the source shape parameter and the destination shape parameter are different.
5. The hardware accelerator according to claim 1 , wherein after tensor transpose is performed, the source shape parameter and the destination shape parameter are different.
6. The hardware accelerator according to claim 1 , wherein tensorflow depth-to-space permutation is achieved by performing tensor transpose, tensor reshape and tensor stride, and tensor reshape and tensor stride.
7. The hardware accelerator according to claim 1 , wherein tensorflow depth-to-space permutation is achieved through a plurality of repeats of tensor stride.
8. The hardware accelerator according to claim 1 , wherein tensorflow space-to-depth permutation is achieved by performing tensor reshape and tensor stride, and tensor reshape and tensor transpose.
9. The hardware accelerator according to claim 1 , wherein tensorflow space-to-depth permutation is achieved through a plurality of repeats of tensor stride.