IP Library Granted Patent US 11,588,239
Granted Patent B2
US 11,588,239 · App. 17/510,086 · Granted Feb 21, 2023

Apparatus and method for providing probabilistic additive gain, calibration, and linearization in a phased array using single bit sources

Inventors: Alex Scott (El Segundo, CA); Harry B. Marr (El Segundo, CA); Michael Borisov (El Segundo, CA); Jason Chaves (El Segundo, CA); Nathan Mintz (El Segundo, CA); Yiu Man So (El Segundo, CA); Daniel G. Thompson (El Segundo, CA); William Dower (El Segundo, CA)
Assignee: EPIRUS, INC.
H01Q3/30H04B7/0617
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Quick Facts
Patent No.
US 11,588,239
App. No.
17/510,086
Granted
Feb 21, 2023
Kind
B2
Abstract

An array of antennae includes a monobit transmitter to insert dither into a transmit signal to form a dithered transmit signal. Monobit receivers process received signals that are combined with the dithered transmit signal to form composite received signals. Digital down converters process the composite received signals to form down converted received signals. A beamformer circuit processes the down converted received signals to form recovered signals.

Claims (44)

1. A radio-frequency (RF) system comprising:

an antenna configured to receive an RF signal;

a transmitter configured to generate a variable dither signal with an amplitude such that a power of the variable dither signal is greater than a power of the RF signal;

a gain controller configured to control an amplitude of the variable dither signal;

a power combiner configured to combine the variable dither signal and the RF signal;

a receiver configured to digitize an output of the power combiner and output a signal; and

an electronic circuitry configured to process the signal from the receiver.

2. The RF system of claim 1 , wherein the transmitter comprises a digital circuitry configured to digitally generate the variable dither signal.

3. The RF system of claim 2 , wherein the transmitter further comprises:

a digital to analog converter (DAC) configured to receive the variable dither signal; and

a balun configured to receive a differential balanced input from the DAC and produce an unbalanced single ended output.

4. The RF system of claim 1 , wherein the transmitter comprises a monobit transmitter.

5. The RF system of claim 1 , wherein the gain controller comprises an automatic gain controller.

6. The RF system of claim 1 , wherein the receiver comprises a monobit receiver.

7. The RF system of claim 1 , wherein the receiver comprises an analog to digital converter (ADC).

8. The RF system of claim 1 , further comprising a balun configured to receive output of the power combiner and provide a balanced output to the electronic circuitry.

9. The RF system of claim 1 , further comprising a switch configured to toggle between a first path connecting the receiver to the electronic circuitry and a second path connecting the transmitter to the electronic circuitry.

10. A radio-frequency (RF) system comprising:

an antenna configured to receive an RF signal;

a transmitter configured to generate a variable dither signal;

a gain controller configured to control an amplitude of the variable dither signal;

a power combiner configured to combine the variable dither signal and the RF signal;

a receiver configured to digitize an output of the power combiner and output a signal; and

an electronic circuitry configured to process the signal from the receiver, the electronic circuitry comprising:

a digital down converter (DDC); and

a digital beamformer.

11. The RF system of claim 10 , wherein the digital beamformer is configured to apply a complex phase shift to a signal output from the digital down converter.

12. The RF system of claim 11 , wherein the digital beamformer is configured to apply the complex phase shift by applying a complex multiplication and a summation.

13. The RF system of claim 10 , further comprising a balun configured to receive output of the power combiner and provide a balanced output to the electronic circuitry.

14. The RF system of claim 10 , further comprising a switch configured to toggle between a first path connecting the receiver to the electronic circuitry and a second path connecting the transmitter to the electronic circuitry.

15. A radio-frequency (RF) system comprising:

an array of antennae;

an array of receivers, a receiver of the array of the receivers configured to digitize an RF signal received by a corresponding antenna of the array of antennae; and

a receiver electronics configured to process signals from the array of receivers, the receiver electronics comprising:

an array of digital down converters (DDCs); and

a digital beamformer configured to apply a complex phase shift to a signal output by the array of digital down converters.

16. The RF system of claim 15 , wherein at least one receiver of the array of receivers comprises a monobit receiver.

17. The RF system of claim 15 , wherein at least one receiver of the array of receivers comprises an analog to digital converter (ADC).

18. The RF system of claim 15 , wherein the digital beamformer is configured to apply the complex phase shift by applying a complex multiplication and a summation.

19. The RF system of claim 15 , wherein the receiver electronics comprises a memory configured to store spatial position of the array of antennae.

20. The RF system of claim 15 , further comprising:

an array of transmitters configured to generate a plurality of variable dither signals;

an array of gain controllers configured to control an amplitude of the plurality of variable dither signals; and

an array of power combiners configured to combine a plurality of RF signals with a plurality of variable dither signal, a power combiner of the array of power combiners corresponding to a receiver of the array of the receivers configured to combine a variable dither signal from the plurality of variable dither signals with the RF signal received by the corresponding antenna of the array of antennae, wherein an output from the power combiner is provided to the receiver of the array of receivers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2021
From: SCOTT, ALEX; MARR, HARRY B.; BORISOV, MICHAEL; CHAVES, JASON; MINTZ, NATHAN; SO, YIU MAN; THOMPSON, DANIEL G.; DOWER, WILLIAM
To: EPIRUS, INC.
Reel/Frame 057966/0037 →
Continuity (3)
Continuation 16995696 · Aug 17, 2020
Provisional Application 62910235 · Oct 3, 2019
Related Publication 20220045423A1 · Feb 10, 2022