High-rate decimation filter with low hardware complexity
A Finite Impulse Response (FIR) filter that reduces the complexity of the hardware required for a filter with a high decimation factor while achieving similar performance of prior art poly-phase filters of greater complexity. The FIR filter includes a small number of multiply-and-accumulate (MAC) units connected in parallel to each other between an input stream and an output stream. The MAC units are provided with coefficients from a memory. In an example implementation, the memory is addressed by a counter and the output of the memory selected by a multiplexer for suppling the coefficients.
1. A finite impulse response (FIR) filter comprising:
a plurality of multiply-and-accumulate (MAC) units connected in parallel to each other between an input stream and an output stream, wherein each of the plurality of MAC unit includes a multiplier connected in series with an adder and an accumulator;
a memory with coefficients for the MAC units;
a first multiplexer connected to the plurality of the MAC units and configured to receive an output of the MAC units and provide an output of one of the MAC units to the output stream;
a coefficient generation circuit that controls the generation of coefficients from the memory comprising a counter and a second multiplexer, wherein:
the counter has C total bits equal to L least significant bits plus M most significant bits, where C, L and M are integers,
the L least significant bits are applied to address the memory and the M most significant bits are applied to the second multiplexer to select a set of coefficients stored at a current address of the memory indicated by the L least significant bits to apply the set of coefficients to the MAC units,
the multiplier is configured to receive an input sample and coefficients from the memory and multiply the input sample with the coefficients to produce a multiplier output to the adder,
the adder is configured to add the multiplier output from the multiplier with a last value stored in a register of the accumulator to produce an accumulator output to the first multiplexer, and
the plurality of MAC units are configured to operate in parallel with each other and the output of one of the MAC units is generated for the output stream periodically based on a decimation factor.
2. The FIR filter of claim 1 , wherein the first multiplexer selects one accumulator periodically based on the decimation factor to provide the output of the selected one accumulator to the output stream, and the one selected accumulator resets its register.
3. The FIR filter of claim 1 , wherein the memory includes N of rows of coefficients where N is equal to the decimation factor, and where each row of the N rows includes a number of coefficients for each of the MAC units.
4. The FIR filter of claim 1 , wherein the M most significant bits select coefficients for each of the MAC units from a row of the memory in a different order for each MAC unit depending on a current value of the M most significant bits.
5. The FIR filter of claim 1 , wherein the plurality of MAC units includes 4 MAC units and the decimation factor is 64.
6. The FIR filter of claim 5 , wherein the multiplexer selects one of accumulator outputs every 64 clocks based on the decimation factor being 64 to provide the output to the output stream, and the one selected accumulator resets its register.
7. The FIR filter of claim 6 , wherein each of the four MAC units receive 12 different coefficients from the memory.
8. The FIR filter of claim 1 , wherein the filter is part of a receiver in a gateway of a satellite communication system.
9. The FIR filter of claim 1 , wherein the input stream has a sampling rate of 59.904 MHz, the output stream has a sampling rate of 936 kHz.
10. A finite impulse response (FIR) filter comprising:
a plurality of multiply-and-accumulate (MAC) units connected in parallel to each other between an input stream and an output stream, wherein each of the plurality of MAC unit includes a multiplier connected in series with an adder and an accumulator;
a memory with N rows of coefficients for the MAC units with each row of the N rows including a number of coefficients for each of the MAC units, wherein N is an integer equal to a decimation factor;
a first multiplexer connected to the plurality of the MAC units and configured to receive an output of the MAC units and provide an output of one of the MAC units to the output stream;
a coefficient generation circuit that controls the generation of coefficients from the memory comprising a counter and a second multiplexer, wherein:
the counter has C total bits equal to L least significant bits plus M most significant bits, where C, L and M are integers, and
the L least significant bits are applied to address the memory and the M most significant bits are applied to the second multiplexer to select a set of coefficients stored at a current address of the memory indicated by the L least significant bits to apply the set of coefficients to the MAC units;
the multiplier is configured to receive an input sample and coefficients from the memory and multiply the input sample with the coefficients to produce a multiplier output to the adder,
the first multiplexer selects one accumulator periodically based on the decimation factor to provide the output of the selected one accumulator to the output stream, and the one selected accumulator resets its register,
the adder is configured to add the multiplier output from the multiplier with a last value stored in a register of the accumulator to produce an accumulator output to the first multiplexer, and
the plurality of MAC units are configured to operate in parallel with each other and the output of one of the MAC units is generated for the output stream periodically based on a decimation factor.
11. The FIR filter of claim 10 , wherein the M most significant bits select coefficients for each of the MAC units from a row of the memory in a different order for each MAC unit depending on a current value of the M most significant bits.
12. The FIR filter of claim 10 , wherein the plurality of MAC units includes 4 MAC units and the decimation factor is 64.
13. The FIR filter of claim 12 , wherein the multiplexer selects one of accumulator outputs every 64 clocks based on the decimation factor being 64 to provide the output to the output stream, and the one selected accumulator resets its register.
14. The FIR filter of claim 12 , wherein:
the input stream has a sampling rate of 59.904 MHz, and
the output stream has a sampling rate of 936 kHz.
15. A finite impulse response (FIR) filter comprising:
a plurality of multiply-and-accumulate (MAC) units connected in parallel to each other between an input stream and an output stream, wherein each of the plurality of MAC unit includes a multiplier connected in series with an adder and an accumulator;
a memory with N rows of coefficients for the MAC units with each row of the N rows including a number of coefficients for each of the MAC units, where N is an integer equal to a decimation factor;
a coefficient generation circuit that controls the generation of coefficients from the memory comprising a counter and a second multiplexer, wherein:
the counter has C total bits equal to L least significant bits plus M most significant bits, where C, L and M are integers, and
the L least significant bits are applied to address the memory and the M most significant bits are applied to the second multiplexer to select a set of coefficients stored at a current address of the memory indicated by the L least significant bits to apply the set of coefficients to the MAC units; and
a first multiplexer connected to the plurality of the MAC units and configured to receive an output of the MAC units and provide an output of one of the MAC units to the output stream, wherein:
the first multiplexer selects one accumulator periodically based on the decimation factor to provide the output of the selected one accumulator to the output stream, and the one selected accumulator resets its register,
the multiplier is configured to receive an input sample and coefficients from the memory and multiply the input sample with the coefficients to produce a multiplier output to the adder,
the adder is configured to add the multiplier output from the multiplier with a last value stored in a register of the accumulator to produce an accumulator output to the first multiplexer,
the plurality of MAC units are configured to operate in parallel with each other and the output of one of the MAC units is generated for the output stream periodically based on a decimation factor,
the plurality of MAC units includes 4 MAC units and the decimation factor is 64, and
the filter is part of a receiver in a gateway of a satellite communication system.
16. The FIR filter of claim 15 , wherein the M most significant bits select coefficients for each of the MAC units from a row of the memory in a different order for each MAC unit depending on a current value of the M most significant bits.
17. The FIR filter of claim 16 , wherein the multiplexer selects one of accumulator outputs every 64 clocks based on the decimation factor being 64 to provide the output to the output stream, and the one selected accumulator resets its register.
18. The FIR filter of claim 17 , wherein each of the four MAC units receive 12 different coefficients from the memory, the input stream has a sampling rate of 59.904 MHz, and the output stream has a sampling rate of 936 kHz.