Engineered nanostructured passivated contacts and method of making the same
The present disclosure relates to a passivating contact that includes a dielectric layer constructed of a first material, an intervening layer constructed of a second material, and a substrate constructed of a semiconductor, where the dielectric layer is positioned between the substrate and the intervening layer, the dielectric layer has a first thickness, and the substrate has a second thickness. The passivating contact also includes a plurality of conductive pathways that include the second material and pass through the first thickness, the second material penetrates into the second thickness forming a plurality of penetrating regions within the substrate, and the plurality of conductive pathways are configured to allow current to pass through the first thickness.
1. A double-side device comprising, in order:
a first silicon layer comprising n-doped polycrystalline silicon;
a first silicon oxide layer having a first thickness;
a second silicon layer comprising n-type crystalline silicon and having a first textured surface and a second textured surface;
a second silicon oxide layer having a second thickness; and
a third silicon layer comprising p-doped polycrystalline silicon, wherein:
a first plurality of conductive pathways comprising the n-doped polycrystalline silicon pass through the first thickness,
a second plurality of conductive pathways comprising the p-doped polycrystalline silicon pass through the second thickness,
the n-doped polycrystalline silicon penetrates into the second silicon layer forming a first plurality of penetrating regions within the second silicon layer, and
the p-doped polycrystalline silicon penetrates into the second silicon layer forming a second plurality of penetrating regions within the second silicon layer.
2. The double-side device of claim 1 , wherein the second silicon layer is between about 0.1 μm and about 1000 μm.
3. The double-side device of claim 1 , wherein at least a portion of the first plurality of penetrating regions penetrate between about 1 nm and about 1000 nm into the second silicon layer.
4. The double-side device of claim 1 , wherein the first silicon oxide layer has a band gap greater than about 2 eV.
5. The double-side device of claim 4 , wherein the band gap is between about 2 eV and about 20 eV.
6. The double-side device of claim 1 , wherein the first silicon oxide layer is configured to passivate the second silicon layer.
7. The double-side device of claim 1 , wherein the first thickness is between 1.9 nm and 50.0 nm.
8. The double-side device of claim 1 , further comprising a layer comprising silicon nitride, wherein the first silicon layer is positioned between the first silicon oxide layer and the layer comprising silicon nitride.