IP Library › Granted Patent US 11,437,984
Granted Patent B2
US 11,437,984 · App. 17/516,726 · Granted Sep 6, 2022

Delay circuit

Inventor: Shigeyuki Okabe (Tokyo, JP)
Assignee: ABLIC Inc.
H03K5/13H03K2005/00195
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Quick Facts
Patent No.
US 11,437,984
App. No.
17/516,726
Granted
Sep 6, 2022
Kind
B2
Abstract

Delay circuit includes: first to fourth transistors; capacitor; constant current source; and resistor. The first transistor has a gate connected to an input terminal, a source connected to the first power supply terminal, and a drain. The second transistor has a gate connected to an input terminal and the gate of the first transistor, a drain connected to the drain of the first transistor and the second terminal of the capacitor, and a source. The third transistor has a gate connected to a node between the drain of the first transistor, the drain of the second transistor, and the second terminal of the capacitor, a source connected to the second power supply terminal, and a drain. The fourth transistor has a gate connected to the node and the gate of the third transistor, a drain connected to the drain of the third transistor and an output terminal, and a source.

Claims (56)

1. A delay circuit including an input terminal and an output terminal, the delay circuit comprising:

a first transistor having a gate connected to the input terminal, a source connected to a first power supply terminal which supplies a first power supply voltage, and a drain;

a capacitor having a first terminal connected to the first power supply terminal and a second terminal connected to the drain of the first transistor;

a second transistor having a gate connected to the gate of the first transistor and the input terminal, a drain connected to the drain of the first transistor and the second terminal of the capacitor, and a source;

a first constant current source connected between the source of the second transistor and a second power supply terminal which supplies a second power supply voltage different from the first power supply voltage;

a third transistor having a gate connected to a node between the drain of the first transistor, the drain of the second transistor, and the second terminal of the capacitor, a source connected to the second power supply terminal, and a drain;

a fourth transistor having a gate connected to the node and the gate of the third transistor, a drain connected to the drain of the third transistor and the output terminal, and a source;

a resistor having a first terminal connected to the source of the fourth transistor and a second terminal connected to the first power supply terminal;

a fifth transistor and a sixth transistor connected between the drain of the fourth transistor and the output terminal; and

a resistance having a first terminal and a second terminal,

the first transistor and the fourth transistor being MOS transistors of a first conductivity type which is one of p-type and n-type,

the second transistor and the third transistor being MOS transistors of a second conductivity type which is the other of p-type and n-type,

the fifth transistor being a MOS transistor of the first conductivity type, the fifth transistor having a gate connected to the drain of the fourth transistor, a source connected to the first power supply terminal, and a drain connected to the first terminal of the resistance,

the sixth transistor being a MOS transistor of the second conductivity type, the sixth transistor having a gate connected to the gate of the fifth transistor and the drain of the fourth transistor, a source connected to the second power supply terminal, and a drain connected to the second terminal of the resistance and the output terminal.

2. The delay circuit according to claim 1 , wherein the resistor is a diode having a first terminal connected to the source of the fourth transistor and a second terminal connected to the first power supply terminal, the delay circuit further comprising:

a seventh transistor having a gate connected to the drain of the sixth transistor, the second terminal of the resistance, and the output terminal, a source connected to the first power supply terminal, and a drain connected to the source of the fourth transistor and the first terminal of the diode.

3. The delay circuit according to claim 2 , wherein a voltage based on a voltage output from the drain of the fourth transistor is supplied to the gate of the seventh transistor.

4. The delay circuit according to claim 3 , further comprising:

a second constant current source connected between the drain of the fourth transistor and the drain of the third transistor.

5. The delay circuit according to claim 2 , further comprising:

a second constant current source connected between the drain of the fourth transistor and the drain of the third transistor.

6. The delay circuit according to claim 1 , wherein the resistor is a diode having a first terminal connected to the source of the fourth transistor and a second terminal connected to the first power supply terminal, the delay circuit fiirther comprising:

a seventh transistor having a gate, a source connected to the first power supply terminal, and a drain connected to the source of the fourth transistor and the first terminal of the diode; and

an inverter having an input terminal connected to the drain of the fourth transistor and an output terminal connected to the gate of the seventh transistor.

7. The delay circuit according to claim 6 , further comprising:

a second constant current source connected between the drain of the fourth transistor and the drain of the third transistor.

8. The delay circuit according to claim 1 , wherein the resistor is a diode having a first terminal connected to the source of the fourth transistor and a second terminal connected to the first power supply terminal, the delay circuit further comprising:

a seventh transistor having a gate, a source connected to the first power supply terminal, and a drain connected to the source of the fourth transistor and the first terminal of the diode, and

a voltage based on a voltage output from the drain of the fourth transistor is supplied to the gate of the seventh transistor.

9. The delay circuit according to claim 8 , further comprising:

a second constant current source connected between the drain of the fourth transistor and the drain of the third transistor.

10. The delay circuit according to claim 1 , further comprising:

a second constant current source connected between the drain of the fourth transistor and the drain of the third transistor.

11. A delay circuit including an input terminal and an output terminal, the delay circuit comprising:

a first transistor having a gate connected to the input terminal, a source connected to a first power supply terminal which supplies a first power supply voltage, and a drain;

a capacitor having a first terminal connected to the first power supply terminal and a second terminal connected to the drain of the first transistor;

a second transistor having a gate connected to the gate of the first transistor and the input terminal, a drain connected to the drain of the first transistor and the second terminal of the capacitor, and a source;

a first constant current source connected between the source of the second transistor and a second power supply terminal which supplies a second power supply voltage different from the first power supply voltage;

a third transistor having a gate connected to a node between the drain of the first transistor, the drain of the second transistor, and the second terminal of the capacitor, a source connected to the second power supply terminal, and a drain;

a fourth transistor having a gate connected to the node and the gate of the third transistor, a drain connected to the drain of the third transistor and the output terminal, and a source; and

a resistor having a first terminal connected to the source of the fourth transistor and a second terminal connected to the first power supply terminal,

the first transistor and the fourth transistor being MOS transistors of a first conductivity type which is one of p-type and n-type,

the second transistor and the third transistor being MOS transistors of a second conductivity type which is the other of p-type and n-type; and

a second constant current source connected between the drain of the fourth transistor and the drain of the third transistor.

12. A delay circuit including an input terminal and an output terminal, the delay circuit comprising:

a first transistor having a gate connected to the input terminal, a source connected to a first power supply terminal which supplies a first power supply voltage, and a drain;

a capacitor having a first terminal connected to the first power supply terminal and a second terminal connected to the drain of the first transistor;

a second transistor having a gate connected to the gate of the first transistor and the input terminal, a drain connected to the drain of the first transistor and the second terminal of the capacitor, and a source;

a first constant current source connected between the source of the second transistor and a second power supply terminal which supplies a second power supply voltage different from the first power supply voltage;

a third transistor having a gate connected to a node between the drain of the first transistor, the drain of the second transistor, and the second terminal of the capacitor, a source connected to the second power supply terminal, and a drain;

a fourth transistor having a gate connected to the node and the gate of the third transistor, a drain connected to the drain of the third transistor and the output terminal, and a source; and

a resistor having a first terminal connected to the source of the fourth transistor and a second terminal connected to the first power supply terminal,

the first transistor and the fourth transistor being MOS transistors of a first conductivity type which is one of p-type and n-type,

the second transistor and the third transistor being MOS transistors of a second conductivity type which is the other of p-type and n-type, wherein the resistor is a diode having a first terminal connected to the source of the fourth transistor and a second terminal connected to the first power supply terminal; and

a seventh transistor having a gate, a source connected to the first power supply terminal, and a drain connected to the source of the fourth transistor and the first terminal of the diode, and

a voltage based on a voltage output from the drain of the fourth transistor is supplied to the gate of the seventh transistor.

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2021
From: OKABE, SHIGEYUKI
To: ABLIC INC.
Reel/Frame 058000/0750 →