IP Library › Granted Patent US 11,720,443

Granted Patent B2

US 11,720,443 · App. 17/518,160 · Granted Aug 8, 2023

Error correction management for a memory device

Inventors: Aaron P. Boehm (Boise, ID); Scott E. Schaefer (Boise, ID)

Assignee: Micron Technology, Inc.

G06F11/1068 G06F11/102 G06F11/1016 G06F12/1425 G11C11/409

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 11,720,443
App. No.: 17/518,160
Granted: Aug 8, 2023
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Methods, systems, and devices for error correction management are described. A system may include a memory device that supports internal detection and correction of corrupted data, and whether such detection and correction functionality is operating properly may be evaluated. A known error may be included (e.g., intentionally introduced) into either data stored at the memory device or an associated error correction codeword, among other options, and data or other indications subsequently generated by the memory device may be evaluated for correctness in view of the error. Thus, either the memory device or a host device coupled with the memory device, among other devices, may determine whether error detection and correction functionality internal to the memory device is operating properly.

Claims (72)

1. A method, comprising:

switching from operating according to a first mode of operation to operating according to a second mode of operation, wherein the second mode of operation is for testing error correcting functionality;

receiving, from a host device, a first command to write a first set of data;

generating a codeword based at least in part on the first command and the first set of data;

receiving, from the host device, a second command to read the first set of data;

altering the codeword corresponding to the first set of data based at least in part on operating according to the second mode of operation;

transmitting, to the host device, a second set of data different than the first set of data in response to the second command and based at least in part on altering the codeword; and

validating functionality of an operation for error correction based at least in part on the second set of data being different than the first set of data.

2. The method of claim 1 , further comprising:

receiving, from the host device, a third command to switch from the first mode of operation to the second mode of operation, wherein switching from operating according to the first mode of operation to operating according to the second mode of operation is based at least in part on the third command.

3. The method of claim 1 , further comprising:

reading, from a mode register at a memory device, respective logic states of one or more bits stored at the mode register, wherein switching from operating according to the first mode of operation to operating according to the second mode of operation is based at least in part on the respective logic states of the one or more bits.

4. The method of claim 1 , further comprising:

identifying an event triggering a switch to the second mode of operation, the event comprising a boot of a memory device or a reboot of the memory device, wherein switching from operating according to the first mode of operation to operating according to the second mode of operation is based at least in part on identifying the event.

5. The method of claim 1 , further comprising:

switching from operating according to the second mode of operation to operating according to the first mode of operation; and

initiating a timer based at least in part on switching from operating according to the second mode of operation to operating according to the first mode of operation, wherein switching from operating according to the first mode of operation to operating according to the second mode of operation is based at least in part on an expiration of the timer.

6. The method of claim 1 , further comprising:

identifying a periodicity associated with the second mode of operation, wherein switching from operating according to the first mode of operation to operating according to the second mode of operation is based at least in part on the periodicity.

7. The method of claim 1 , further comprising:

writing the codeword to a memory device based at least in part on the generating; and

accessing the codeword based at least in part on the second command, wherein altering the codeword comprises altering, based at least in part on accessing the codeword, at least one bit of the codeword to generate an altered version of the codeword.

8. The method of claim 1 , further comprising:

generating an altered version of the codeword based at least in part on the first command and the first set of data;

writing the altered version of the codeword to a memory device based at least in part on the generating; and

accessing the altered version of the codeword based at least in part on the second command.

9. A method, comprising:

receiving, from a host device, a first command to write a first set of data;

writing, based at least in part on the first command, the first set of data to a first location within a memory device;

receiving, from the host device, a third command to write an altered version of the first set of data;

altering the first set of data or a codeword corresponding to the first set of data based at least in part on operating according to the second mode of operation;

writing, based at least in part on the third command, the altered version of the first set of data to the first location within the memory device, wherein writing the altered version of the first set of data overwrites at least some of the first set of data;

receiving, from the host device, a second command to read the first set of data; and

transmitting, to the host device, a second set of data in response to the second command and based at least in part on altering the first set of data or the codeword.

10. The method of claim 9 , further comprising:

writing, based at least in part on the first command, the codeword to a second location within the memory device; and

blocking the second location within the memory device from being accessed in response to the third command and based at least in part on writing the codeword to the second location.

11. The method of claim 9 , further comprising:

generating, based at least in part on the third command, a second codeword that corresponds to the altered version of the first set of data; and

refraining from writing the second codeword to the memory device based at least in part on operating according to the second mode of operation.

12. The method of claim 1 , further comprising:

inverting a logic state of at least one bit of the first set of data or the codeword, wherein altering the codeword comprises inverting the logic state of the at least one bit of the codeword.

13. The method of claim 1 , further comprising:

performing the operation for error correction based at least in part on the second command, wherein performing the operation for error correction comprises generating the second set of data based at least in part on the altered codeword; and

transmitting one or more commands to the host device based at least in part on the operation for error correction.

14. A method, comprising:

transmitting, to a memory device, a first command to switch from a first mode of operation to a second mode of operation, wherein the second mode of operation is for testing error correcting functionality;

transmitting, to the memory device, a second command to write a first set of data;

transmitting, to the memory device, a third command to read the first set of data based at least in part on transmitting the first command to switch the memory device to the second mode of operation;

receiving, from the memory device and in response to the third command, a second set of data different than the first set of data, the second set of data based at least in part on an altered version of a codeword corresponding to the first set of data, wherein receiving the second set of data is based at least in part on transmitting the first command to switch the memory device to the second mode of operation; and

validating functionality of an operation for error correction based at least in part on the second set of data being different than the first set of data.

15. The method of claim 14 , further comprising:

setting one or more bits stored at a mode register of the memory device to a respective logic state corresponding to the second mode of operation based at least in part on the first command to switch the memory device to the second mode of operation.

16. The method of claim 14 , further comprising:

determining that the second set of data is different than the first set of data, wherein validating functionality of the operation for error correction is based at least in part on determining that the second set of data is different than the first set of data.

17. The method of claim 14 , further comprising:

transmitting, to the memory device, a fourth command to write an altered version of the first set of data, wherein transmitting the third command occurs after transmitting the fourth command.

18. An apparatus, comprising:

a first array of memory cells to store data;

a second array of memory cells to store codewords associated with the data;

an encoder coupled with the second array of memory cells and configured to generate the codewords associated with the data; and

logic coupled with the first array of memory cells and the second array of memory cells and operable to cause the apparatus to:

switch from operating according to a first mode of operation to operating according to a second mode of operation, wherein the second mode of operation is for testing error correcting functionality;

receive first signaling indicative of a first command to write a first set of data to the first array of memory cells;

generate a codeword based at least in part on the first command and the first set of data;

receive second signaling indicative of a second command to read the first set of data from the first array of memory cells;

alter the codeword generated by the encoder and corresponding to the first set of data based at least in part on operating according to the second mode of operation;

transmit third signaling indicative of a second set of data different than the first set of data in response to the second command and based at least in part on altering the codeword; and

validate functionality of an operation for error correction based at least in part on the second set of data being different than the first set of data.

19. The apparatus of claim 18 , wherein the logic is further operable to cause the apparatus to:

invert at least one bit of the first set of data or the codeword based at least in part on altering the first set of data or the codeword.