Vertical transistors having improved control of parasitic capacitance and gate-to-contact short circuits
Embodiments of the invention are directed to a method of forming an integrated circuit (IC). The method includes performing fabrication operations that form the IC. The fabrication operations include forming a channel fin. A gate structure is formed along a sidewall surface of the channel fin. The gate structure includes a conductive gate having an L-shape profile, and the L-shape profile includes a conductive gate foot region. The conductive gate foot region is replaced with a dielectric foot region.
1 . A method of forming an integrated circuit (IC), the method comprising performing fabrication operations that form the IC, wherein the fabrication operations comprise:
forming a channel fin;
forming a gate structure along a sidewall surface of the channel fin;
wherein the gate structure comprises a conductive gate having an L-shape profile;
wherein the L-shape profile comprises a conductive gate leg region and a conductive gate foot region, the conductive gate foot region comprising a conductive gate foot region top surface extending over an entirety of the conductive gate foot region and intersecting a sidewall of the conductive gate leg region;
forming a protective liner along the sidewall of the conductive gate leg region, such that an entirety of a bottom surface of the protective liner extends over an entirety of the conductive gate foot region top surface; and
replacing the entirety of the conductive gate foot region with a dielectric foot region such that a space that was occupied by the conductive gate foot region is occupied by the dielectric foot region;
wherein at least a portion of the space that was occupied by the conductive gate foot region is defined by a portion of the protective liner and a portion of the conductive gate leg region.
2 . The method of claim 1 , wherein the conductive gate leg region is along the sidewall surface of the channel fin.
3 . The method of claim 1 , wherein the conductive gate comprises a work function metal.
4 . The method of claim 1 , wherein the dielectric foot region is non-sacrificial in that the dielectric foot region is present in a final version of the IC.
5 . The method of claim 3 , wherein the work function metal comprises a p-type work function metal or an n-type work function metal.
6 . The method of claim 2 , wherein the fabrication operations further comprise:
forming a bottom source or drain (S/D) region communicatively coupled to a bottom end region of the channel fin; and
forming a bottom S/D contact communicatively coupled to the bottom S/D region;
wherein the dielectric foot region is between a portion of the conductive gate leg and a portion of the bottom S/D contact.
7 . A method of forming an integrated circuit (IC), the method comprising performing fabrication operations that form the IC, wherein the fabrication operations comprise:
forming a first channel fin;
forming a second channel fin;
forming a first gate structure along a sidewall surface of the first channel fin;
wherein the first gate structure comprises a first conductive gate having a first L-shape profile;
wherein the first L-shape profile comprises a first conductive gate leg region and a first conductive gate foot region, the first conductive gate foot region comprising a first conductive gate foot region top surface extending over an entirety of the first conductive gate foot region and intersecting a sidewall of the first conductive gate leg region;
forming a first protective liner along the sidewall of the first conductive gate leg region, such that an entirety of a bottom surface of the first protective liner extends over an entirety of the first conductive gate foot region top surface;
forming a second gate structure along a sidewall surface of the second channel fin;
wherein the second gate structure comprises a second conductive gate having a second L-shape profile;
wherein the second L-shape profile comprises a second conductive gate leg region and a second conductive gate foot region, the second conductive gate foot region comprising a second conductive gate foot region top surface extending over an entirety of the second conductive gate foot region and intersecting a sidewall of the second conductive gate leg region;
forming a second protective liner along the sidewall of the second conductive gate leg region, such that an entirety of a bottom surface of the second protective liner extends over an entirety of the second conductive gate foot region top surface;
replacing the entirety of the first conductive gate foot region with a first dielectric foot region such that a space that was occupied by the first conductive gate foot region is occupied by the first dielectric foot region;
wherein at least a portion of the space that was occupied by the first conductive gate foot region is defined by a portion of the first protective liner and a portion of the first conductive gate leg region; and
replacing the entirety of the second conductive gate foot region with a second dielectric foot region such that a space that was occupied by the second conductive gate foot region is occupied by the second dielectric foot region;
wherein at least a portion of the space that was occupied by the second conductive gate foot region is defined by a portion of the second protective liner and a portion of the second conductive gate leg region.
8 . The method of claim 7 , wherein:
the first conductive gate leg region is along the sidewall surface of the first channel fin; and
the second conductive gate leg region is along the sidewall surface of the second channel fin.
9 . The method of claim 7 , wherein the first conductive gate and the second conductive gate comprise a work function metal.
10 . The method of claim 7 , wherein the first dielectric foot region and the second dielectric foot region are non-sacrificial in that the first dielectric foot region and the second dielectric foot region are present in a final version of the IC.
11 . The method of claim 9 , wherein the work function metal comprises a p-type work function metal or an n-type work function metal.
12 . The method of claim 8 , wherein a portion of the first dielectric foot region and a portion of the second dielectric foot region are between a bottom region of the first conductive gate leg region and a bottom region of the second conductive gate leg region.
13 . The method of claim 8 , wherein the fabrication operations further comprise:
forming a shared bottom source or drain (S/D) region communicatively coupled to a bottom end region of the first channel fin and a bottom end region of the second channel fin; and
forming a bottom S/D contact communicatively coupled to the shared bottom S/D region;
wherein the first dielectric foot region and the second dielectric foot region are between:
a portion of the first conductive gate leg and a portion of the shared bottom S/D contact; and
a portion of the second conductive gate leg and the portion of the shared bottom S/D contact.
14 . An integrated circuit (IC) comprising:
a first channel fin; and
a first gate structure along a sidewall surface of the first channel fin;
wherein the first gate structure comprises a first conductive gate having a first L-shape profile;
wherein the first L-shape profile comprises a first conductive gate leg region and a first dielectric foot region, the first dielectric foot region comprising a first dielectric foot region top surface extending over an entirety of the first dielectric foot region and intersecting a sidewall of the first conductive gate leg region; and
a first protective liner along the sidewall of the first conductive gate leg region, such that an entirety of a bottom surface of the first protective liner extends over an entirety of the first dielectric foot region top surface;
wherein a space occupied by the first dielectric foot region was previously occupied by a removed first conductive gate foot region; and
wherein at least a portion of the space that was occupied by the removed first conductive gate foot region is defined by a portion of the first protective liner and a portion of the first conductive gate leg region.
15 . The IC of claim 14 further comprising:
a second channel fin; and
a second gate structure along a sidewall surface of the second channel fin;
wherein the second gate structure comprises a second conductive gate having a second L-shape profile;
wherein the second L-shape profile comprises a second conductive gate leg region and a second dielectric foot region, the second dielectric foot region comprising a second dielectric foot region top surface extending over an entirety of the second dielectric foot region and intersecting a sidewall of the second conductive gate leg region; and
a second protective liner along the sidewall of the second conductive gate leg region, such that an entirety of a bottom surface of the second protective liner extends over an entirety of the second dielectric foot region top surface;
wherein a space occupied by the second dielectric foot region was previously occupied by a removed second conductive gate foot region; and
wherein at least a portion of the space that was occupied by the removed second conductive gate foot region is defined by at portion of the second protective liner and a portion of the second conductive gate leg region.
16 . The IC of claim 15 , wherein the first conductive gate and the second conductive gate comprise a work function metal.
17 . The IC of claim 15 , wherein the first dielectric foot region and the second dielectric foot region are non-sacrificial in that the first dielectric foot region and the second dielectric foot region are present in a final version of the IC.
18 . The IC of claim 16 , wherein the work function metal comprises a p-type work function metal or an n-type work function metal.
19 . The IC of claim 15 , wherein a portion of the first dielectric foot region and a portion of the second dielectric foot region are between a bottom region of the first conductive gate leg region and a bottom region of the second conductive gate leg region.
20 . The IC of claim 15 further comprising:
a shared bottom source or drain (S/D) region communicatively coupled to a bottom end region of the first channel fin and a bottom end region of the second channel fin; and
a bottom S/D contact communicatively coupled to the shared bottom S/D region;
wherein the first dielectric foot region and the second dielectric foot region are between:
a portion of the first conductive gate leg and a portion of the shared bottom S/D contact; and
a portion of the second conductive gate leg and the portion of the shared bottom S/D contact.