Bus arbitration circuit and data transfer system including the same
A bus arbitration circuit includes a first bus port, a second bus port, a first output circuit connected to the first bus port, a second output circuit connected to the second bus port, a control circuit, and a switch circuit. The control circuit includes a first input port, a second input port, a control signal output port, and an output port. The first input port receives data of the first bus port, the second input port receives data of the second bus port, and data is outputted from the output port to an input port of the first output circuit. The switch circuit has an input port connected to the first bus port, a control port connected to the control signal output port of the control circuit, and an output port from which data of a host bus is outputted to an input port of the second output circuit.
1. A bus arbitration circuit comprising:
a first bus port connected to a host bus;
a second bus port connected to a local bus;
a first output circuit having an output port connected to the first bus port;
a second output circuit having an output port connected to the second bus port;
a control circuit comprising a first input port, a second input port, a control signal output port, and an output port, wherein the first input port receives data of the first bus port, the second input port receives data of the second bus port, and data is outputted from the output port of the control circuit to an input port of the first output circuit; and
a switch circuit having an input port connected to the first bus port, a control port connected to the control signal output port of the control circuit, and an output port from which data of the host bus is outputted to an input port of the second output circuit,
wherein the switch circuit is set to a closed state by a control signal of the control circuit in a standby state, and outputs a start condition signal received at the input port,
wherein the control circuit sets the switch circuit to an open state by the control signal after a predetermined time elapses, in response to the start condition signal being received at the first input port in the standby state.
2. The bus arbitration circuit according to claim 1 , comprising:
a flip-flop circuit provided between the second input port of the control circuit and the second bus port,
wherein the flip-flop circuit has an input port receiving data of the second bus port, a clock port receiving a clock signal from the control circuit, and an output port connected to the second input port of the control circuit.
3. The bus arbitration circuit according to claim 1 , wherein the first output circuit and the second output circuit are composed of NMOS transistors.
4. The bus arbitration circuit according to claim 2 , wherein the first output circuit and the second output circuit are composed of NMOS transistors.
5. A data transfer system comprising:
a master IC and a slave IC connected to a host bus;
the bus arbitration circuit according to claim 1 connected to the host bus;
a local bus connected to the bus arbitration circuit; and
a slave IC connected to the local bus.
6. A data transfer system comprising:
a master IC and a slave IC connected to a host bus;
the bus arbitration circuit according to claim 2 connected to the host bus;
a local bus connected to the bus arbitration circuit; and
a slave IC connected to the local bus.
7. A data transfer system comprising:
a master IC and a slave IC connected to a host bus;
the bus arbitration circuit according to claim 3 connected to the host bus;
a local bus connected to the bus arbitration circuit; and
a slave IC connected to the local bus.