Multi-state programming of memory cells
The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.
1. An apparatus, comprising:
a memory having a plurality of memory cells; and
circuitry configured to program a memory cell of the plurality of memory cells to one of at least three possible data states by:
applying a voltage pulse to the memory cell;
determining the memory cell snaps back in response to the applied voltage pulse;
turning off a current to the memory cell upon determining the memory cell snaps back; and
applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell, wherein each of the number of additional voltage pulses have a same magnitude.
2. The apparatus of claim 1 , wherein one of the at least three possible data states is associated with a threshold voltage distribution whose magnitude is greater for a first polarity than a second polarity.
3. The apparatus of claim 2 , wherein an additional one of the at least three possible data states is associated with an additional threshold voltage distribution whose magnitude is greater for the second polarity than the first polarity.
4. The apparatus of claim 1 , wherein one of the at least three possible data states is associated with a threshold voltage distribution whose magnitude is substantially equal for a first polarity and a second polarity.
5. The apparatus of claim 1 , wherein one of the at least three possible data states is associated with a symmetric threshold voltage distribution.
6. The apparatus of claim 1 , wherein the at least three possible data states comprise six possible data states.
7. The apparatus of claim 1 , wherein the number of additional voltage pulses comprise four additional voltage pulses.
8. The apparatus of claim 1 , wherein the number of additional voltage pulses comprise six additional voltage pulses.
9. An apparatus, comprising:
a memory having a plurality of memory cells; and
circuitry configured to program a memory cell of the plurality of memory cells to one of at least three possible data states by:
applying a voltage pulse to the memory cell;
determining the memory cell snaps back in response to the applied voltage pulse;
turning off a current to the memory cell upon determining the memory cell snaps back; and
applying a single additional voltage pulse to the memory cell after turning off the current to the memory cell, wherein a duration of the single additional voltage pulse is shorter than a duration of the voltage pulse, and wherein the single additional voltage pulse has a same magnitude for the duration of the single additional voltage pulse.
10. The apparatus of claim 9 , wherein each of the plurality of memory cells is a self-selecting memory cell.
11. The apparatus of claim 9 , wherein the duration of the single additional voltage pulse is five nanoseconds.
12. The apparatus of claim 9 , wherein the voltage pulse and the single additional voltage pulse have a same magnitude.
13. The apparatus of claim 9 , wherein applying the single additional voltage to the memory cell increases a threshold voltage of the memory cell.
14. The apparatus of claim 9 , wherein applying the single additional voltage to the memory cell decreases a threshold voltage of the memory cell.
15. A method of operating memory, comprising:
programming a memory cell to one of at least three possible data states by:
applying a voltage pulse to the memory cell;
determining the memory cell snaps back in response to the applied voltage pulse;
turning off a current to the memory cell upon determining the memory cell snaps back; and
applying one additional voltage pulse to the memory cell after turning off the current to the memory cell, wherein the one additional voltage pulse has a same magnitude for a duration of the one additional voltage pulse; or
applying two additional voltage pulses to the memory cell after turning off the current to the memory cell, wherein each of the two additional voltage pulses have a same magnitude.
16. The method of claim 15 , wherein the one additional voltage pulse has a first polarity or a second polarity that is opposite the first polarity.
17. The method of claim 15 , wherein each of the two additional voltage pulses have a same polarity.
18. The method of claim 15 , wherein the at least three possible data states comprise four possible data states.
19. The method of claim 15 , wherein the method includes determining the memory cell snaps back using a sense amplifier.
20. The method of claim 15 , wherein the method includes determining the memory cell snaps back by determining that a voltage on a signal line coupled to the memory cell meets or exceeds a particular voltage threshold.