Vector processor data storage
Aspects of the present disclosure provide an aligned storage strategy for stripes within a long vector for a vector processor, such that the extra computation needed to track strides between input stripes and output stripes may be eliminated. As a result, the stripe locations are located in a more predictable memory access pattern such that memory access bandwidth may be improved and the tendency for memory error may be reduced.
1. A device comprising:
a vector processor configured to:
receive as an input one of a first vector and a second vector,
provide as an output, based at least in part on the input, the other one of the first vector and the second vector wherein the second vector is longer than the first vector and
split the second vector into a plurality of stripes; and
one or more computer memory units implementing a buffer comprising a plurality of lines, configured to store the second vector in the plurality of stripes, wherein a first stripe of the plurality of stripes and a second stripe of the plurality of stripes are aligned in the buffer on separate lines of the plurality of lines.
2. The device of claim 1 , wherein
the first vector is the input for the vector processor, and
the second vector is the output for the vector processor.
3. The device of claim 1 , wherein
the first vector is the output for the vector processor, and
the second vector is the input for the vector processor.
4. The device of claim 1 , wherein
the first stripe starts on a first line of the plurality of lines, and the second stripe starts on a second line of the plurality of lines that is adjacent the first line.
5. The device of claim 1 , wherein
the second stripe is interleaved with the first stripe.
6. The device of claim 1 , wherein the buffer is divided into K sections, wherein K is an integer, and
the first stripe and the second stripe are stored in different sections of the K sections.
7. The device of claim 6 , wherein K is two, and
the first stripe is located from the second stripe by one half a size of the buffer.
8. The device of claim 6 , wherein K is two, the second vector comprises more than two stripes, and wherein
the plurality of stripes are stored in alternating sections of the two sections.
9. The device of claim 1 , wherein the buffer is further configured to store the first vector.
10. A method to store input and output vectors for a vector processor in one or more computer memory units implementing a buffer, the method comprising:
receiving, by the vector processor, one of a first vector and a second vector as input to the vector processor;
providing, with the vector processor, the other one of the first vector and second vector as output of the vector processor, wherein the second vector is longer than the first vector;
splitting, with the vector processor, the second vector into a plurality of stripes; and
storing the second vector in the plurality of stripes in the buffer, wherein the buffer comprises a plurality of lines and storing comprises:
aligning a first stripe of the plurality of stripes and a second stripe of the plurality of stripes by storing the first and second stripes on separate lines of the plurality of lines.
11. The method of claim 10 , wherein
the first vector is an input vector for the vector processor, and
the second vector is an output vector for the vector processor.
12. The method of claim 10 , wherein
the first vector is an output vector for the vector processor, and
the second vector is an input vector for the vector processor.
13. The method of claim 10 , wherein
Storing the second vector further comprises:
storing the first stripe starting on a first line of the plurality of lines, and
storing the second stripe starting on a second line of the plurality of lines that is adjacent the first line.
14. The method of claim 10 , wherein storing the second vector further comprises:
interleaving the second stripe with the first stripe.
15. The method of claim 10 , further comprising:
dividing the buffer into K sections, wherein K is an integer, wherein
storing the second vector comprises storing the first stripe and the second stripe in different sections of the K sections.
16. The method of claim 15 , wherein K is two, and storing the second vector further comprises:
spacing the first stripe from the second stripe by one half a size of the buffer.
17. The method of claim 15 , wherein K is two, the second vector comprises more than two stripes, and storing the second vector further comprises:
alternatingly storing the plurality of stripes in the two sections.
18. The method of claim 10 , further comprising:
storing the first vector in the buffer.
19. A system comprising at least one processor and at least one computer-readable storage medium having stored thereon instructions which, when executed, program the at least one processor to perform a method for storing input and output vectors of a vector processor in one or more computer memory units implementing a buffer, the method comprising acts of:
receiving, by the vector processor, one of a first vector and a second vector as input to the vector processor;
providing, with the vector processor, the other one of the first vector and second vector as output of the vector processor, wherein the second vector is longer than the first vector;
splitting, with the vector processor, the second vector into a plurality of stripes; and
storing the second vector in the plurality of stripes in the buffer, wherein the buffer comprises a plurality of lines and storing comprises:
aligning a first stripe of the plurality of stripes and a second stripe of the plurality of stripes by storing the first and second stripes on separate lines of the buffer.
20. The system of claim 19 , wherein the act of storing the second vector further comprises:
interleaving the second stripe with the first stripe.