Laser driver with pulse scaling circuit for laser displays
A laser driver includes a pulse generator circuit, a pulse scaling circuit, and a power stage circuit. The pulse generator circuit generates a first voltage pulse of a first duration. The pulse scaling circuit includes a first transistor with a first gate electrode receiving the first voltage pulse, a capacitor having an electrode connected to a common terminal of a pair of resistors connected in series with the first transistor, and a second transistor with a second gate electrode connected to the first gate electrode and a second drain electrode coupled to a supply voltage via a resistor. Responsive to the reception of the first voltage pulse, a second voltage pulse of a second duration shorter than the first duration is generated at the second drain electrode. The power stage circuit converts the second voltage pulse into a current pulse driving at least one emission element of a laser display.
1. A pulse scaling circuit comprising:
a first transistor with a first gate electrode receiving an input pulse of a first duration;
a capacitor having an electrode connected to a common terminal of a pair of resistors connected in series with the first transistor; and
a second transistor with a second gate electrode connected to the first gate electrode and a second drain electrode coupled to a supply voltage via a resistor, wherein,
responsive to the reception of the input pulse, an output pulse of a second duration shorter than the first duration is generated at the second drain electrode.
2. The pulse scaling circuit of claim 1 , further comprising a third transistor connected in series with the second transistor, a third gate electrode of the third transistor connected to the electrode of the capacitor.
3. The pulse scaling circuit of claim 2 , wherein a ratio between a first resistance of a first resistor in the pair and a second resistance of a second resistor in the pair is such that a voltage at the electrode of the capacitor at an end of a discharge cycle of the capacitor is below a threshold voltage of the third gate electrode.
4. The pulse scaling circuit of claim 2 , wherein the second and third transistors are turned on at an end of the input pulse.
5. The pulse scaling circuit of claim 2 , wherein the output pulse lasts until a voltage at the electrode of the capacitor becomes lower than a threshold voltage of the third gate electrode.
6. The pulse scaling circuit of claim 1 , wherein the input pulse coincides with a charge cycle of the capacitor, and the output pulse coincides with a discharge cycle of the capacitor following the charge cycle.
7. The pulse scaling circuit of claim 1 , wherein:
the capacitor is charged during a charge cycle with a charge current flowing through a first resistor in the pair, the input pulse causing the first transistor and the second transistor to be turned off during the charge cycle; and
the capacitor is discharged during a discharge cycle following the charge cycle with a discharge current flowing through a second resistor in the pair and the first transistor.
8. The pulse scaling circuit of claim 7 , wherein a ratio between a first resistance of the first resistor and a second resistance of the second resistor causes that a ratio between an average value of the charge current and an average value of the discharge current corresponds to a ratio between the first duration and the second duration.
9. The pulse scaling circuit of claim 1 , wherein the first duration and the second duration are in the order of nanoseconds or below 1 nanosecond.
10. The pulse scaling circuit of claim 1 , wherein each of the first transistor and the second transistor is a Gallium Nitride field-effect transistor (GaN FET).
11. A laser driver comprising:
a pulse generator circuit configured to generate a first voltage pulse of a first duration;
a pulse scaling circuit coupled to the pulse generator circuit, the pulse scaling circuit comprising:
a first transistor with a first gate electrode receiving the first voltage pulse,
a capacitor having an electrode connected to a common terminal of a pair of resistors connected in series with the first transistor, and
a second transistor with a second gate electrode connected to the first gate electrode and a second drain electrode coupled to a supply voltage via a resistor, wherein,
responsive to the reception of the first voltage pulse, a second voltage pulse of a second duration shorter than the first duration is generated at the second drain electrode; and
a power stage circuit coupled to the pulse scaling circuit, the power stage circuit configured to convert the second voltage pulse into a current pulse driving at least one emission element of a laser display.
12. The laser driver of claim 11 , wherein the at least one emission element driven by the current pulse emits one or more light beams in a spread spectrum mitigating a level of coherence artifacts of light emitted from the laser display.
13. The laser driver of claim 11 , wherein the at least one emission element comprises at least one laser diode.
14. The laser driver of claim 11 , wherein the laser driver is integrated into a headset, and the laser driver initiates emission of image light from the laser display integrated into the headset.
15. The laser driver of claim 11 , wherein the power stage circuit comprises a current source based on a pulse-width modulation (PWM) controller with a voltage feedback loop and a current feedback loop.
16. The laser driver of claim 11 , wherein the pulse scaling circuit further comprising a third transistor connected in series with the second transistor, a third gate electrode of the third transistor connected to the electrode of the capacitor.
17. The laser driver of claim 16 , wherein:
the second and third transistors are turned on at an end of the first voltage pulse; and
the second voltage pulse lasts until a voltage at the electrode of the capacitor becomes lower than a threshold voltage of the third gate electrode.
18. The laser driver of claim 11 , wherein:
the capacitor is charged during a charge cycle with a charge current flowing through a first resistor in the pair, the first voltage pulse causing the first transistor and the second transistor to be turned off during the charge cycle;
the capacitor is discharged during a discharge cycle following the charge cycle with a discharge current flowing through a second resistor in the pair and the first transistor; and
a ratio between a first resistance of the first resistor and a second resistance of the second resistor causes that a ratio between an average value of the charge current and an average value of the discharge current corresponds to a ratio between the first duration and the second duration.
19. A method comprising:
receiving an input pulse of a first duration at a first gate electrode of a first transistor;
charging a capacitor during the first duration, the capacitor having an electrode connected to a common terminal of a pair of resistors connected in series with the first transistor; and
discharging the capacitor to generate an output pulse of a second duration shorter than the first duration at a second drain electrode of a second transistor, a second gate electrode of the second transistor connected to the first gate electrode and the second drain electrode coupled to a supply voltage via a resistor.
20. The method of claim 19 , further comprising:
charging the capacitor during a charge cycle with a charge current flowing through a first resistor in the pair, the input pulse causing the first transistor and the second transistor to be turned off during the charge cycle; and
discharging the capacitor during a discharge cycle following the charge cycle with a discharge current flowing through a second resistor in the pair and the first transistor, wherein
a ratio between a first resistance of the first resistor and a second resistance of the second resistor causes that a ratio between an average value of the charge current and an average value of the discharge current corresponds to a ratio between the first duration and the second duration.