IP Library Granted Patent US 11,824,927
Granted Patent B2
US 11,824,927 · App. 17/531,481 · Granted Nov 21, 2023

Partial timestamps

Inventor: Peter William Longhurst (Burnaby, CA)
Assignee: Teradici Co.
H04L67/1095
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Quick Facts
Patent No.
US 11,824,927
App. No.
17/531,481
Granted
Nov 21, 2023
Kind
B2
Abstract

In some examples, an electronic device includes a processor to determine a threshold magnitude. Based on the threshold magnitude, the processor is to determine a bit mapping for a partial timestamp. The partial timestamp is a sequence of bits of a timestamp that is based on a clock signal of the processor. The processor is to determine the partial timestamp based on the bit mapping and the timestamp, append the partial timestamp to a data signal, and cause transmission of the data signal.

Claims (37)

1. An electronic device, comprising:

a processor to:

determine a threshold magnitude;

determine, based on the threshold magnitude, a bit mapping for a partial timestamp, the partial timestamp a sequence of bits of a timestamp that is based on a clock signal of the processor, wherein a magnitude of the bit mapping is equivalent to or less than the threshold magnitude;

determine the partial timestamp based on the bit mapping and the timestamp;

append the partial timestamp to a data signal; and

cause transmission of the data signal.

2. The electronic device of claim 1 , wherein to determine the threshold magnitude, the processor is to determine a number of unused bits in a portion of the data signal that has a fixed size across multiple data signals.

3. The electronic device of claim 1 , wherein to determine the bit mapping for the partial timestamp, the processor is to:

determine a lower time threshold;

determine an upper time threshold; and

determine the bit mapping based on the lower time threshold and the upper time threshold.

4. The electronic device of claim 3 , wherein the partial timestamp is equivalent to an overlap of a portion of the timestamp and the bit mapping, the overlap including a first bit associated with the lower time threshold and a second bit associated with the upper time threshold.

5. An electronic device, comprising:

a processor to:

receive a first data signal that includes a first partial timestamp and a second data signal that includes a second partial timestamp;

determine a first corrected elapsed time and a second corrected elapsed time based on the first partial timestamp and the second partial timestamp, respectively, wherein to determine the first corrected elapsed time, the processor is to utilize a system-level clock of the electronic device to generate a timestamp; and

responsive to a determination that first corrected elapsed time is equivalent to the second corrected elapsed time, synchronize the first data signal and the second data signal.

6. The electronic device of claim 5 , wherein to determine the first corrected elapsed time, the processor is to:

determine an uncorrected elapsed time by subtracting an origin time from the timestamp;

rounding the uncorrected elapsed time to a nearest upper time threshold; and

adding a result of the rounding and the first partial timestamp.

7. The electronic device of claim 6 , wherein the origin time is a start time for a remote session.

8. The electronic device of claim 6 , wherein an upper time threshold is a time period that defines a networking delay tolerance, a signal processing delay, or a combination thereof, that the electronic device is able to compensate for without loss of data.

9. A non-transitory machine-readable medium storing machine-readable instructions, which, when executed by a processor, cause the processor to:

receive a data signal that includes a partial timestamp;

determine whether the data signal is a first data signal of a remote session;

generate, responsive to a determination that the data signal is the first data signal of the remote session, an origin time for the remote session;

determine, utilizing the origin time and the partial timestamp, a corrected elapsed time,

wherein, to determine the corrected elapsed time, the processor is to generate a time stamp;

determine an uncorrected elapsed time by subtracting the origin time from the timestamp;

round the uncorrected elapsed time to a nearest upper time threshold; and

add a result of the rounding and the partial timestamp; and

synchronize the data signal with other signals of the remote session having the corrected elapsed time.

10. The non-transitory machine-readable medium of claim 9 , wherein, responsive to the determination that the data signal is the first data signal of the remote session, the processor is to set a counter to zero.

11. The non-transitory machine-readable medium of claim 10 , wherein, responsive to rounding the uncorrected elapsed time downward, the processor is to decrement a counter; and wherein, responsive to rounding the uncorrected elapsed time upward, the processor is to increment the counter.

12. The non-transitory machine-readable medium of claim 11 , wherein, to synchronize the data signal with other signals of the remote session having the corrected elapsed time, the processor is to cause a display device, an audio device, or a combination thereof, to display, play, or a combination thereof, the data signal with the other signals having the same corrected elapsed time within a same interval, the interval indicated by the counter.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2025
From: TERADICI CO.
To: HP TECHNOLOGY HOLDINGS LLC
Reel/Frame 071854/0373 →
CHANGE OF NAME Recorded May 19, 2025
From: TERADICI CORPORATION
To: TERADICI CO.
Reel/Frame 071296/0559 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2023
From: LONGHURST, PETER
To: TERADICI CO.
Reel/Frame 065210/0778 →
Continuity (1)
Related Publication 20230164217A1 · May 25, 2023