CMOS circuit

1. A CMOS integrated circuit comprising:

digital-to-analogue converters (DACs);

analogue-to-digital converters (ADCs);

a digital signal processor (DSP);

on-chip switching;

an on-chip processor; and

logic enabling the CMOS integrated circuit to:

receive data from a plurality of data sources in a 5G network;

combine the data from the plurality of data sources into a single data stream;

encode the single data stream using the DSP; and

cause the encoded single data stream to be transmitted to another device in the 5G network,

wherein the transmission is over a transmission medium, and

wherein the transmission medium is chosen from the group consisting of an optical link, a mm Wave link, a radio link, and a SERDES link.

2. The CMOS integrated circuit of claim 1 wherein the logic further enables the CMOS integrated circuit to:

receive a data stream in a 5G network from the transmission medium;

decode the data stream;

divide the data stream into a plurality of divided data streams; and

cause each divided data stream to be transmitted to a respective data source of the plurality of data sources.

3. The CMOS integrated circuit of claim 2 , wherein the plurality of data sources are respective antenna heads of an RU.

4. The CMOS integrated circuit of claim 2 , wherein the CMOS integrated circuit causes the encoded single data stream to be transmitted to another device in the 5G network over millimeter wave transmissions over the mm Wave link, and

wherein the logic enables the CMOS integrated circuit to encode the data stream using complex modulation.

5. The CMOS integrated circuit of claim 2 , wherein the data sources are millimeter wave transmissions,

encoded using complex modulation, and wherein the logic enables the CMOS integrated circuit to:

convert the encoded data into a digital format;

combine the digitally converted encoded data; and

convert the combined digitally converted encoded data into a complex encoded signal.

6. The CMOS integrated circuit of claim 5 , wherein the complex encoded signal is encoded on a light wave for transmission across the optical link using a complex modulation scheme such as QAM, and

wherein the CMOS integrated circuit further comprises 2 DACs and 2 ADCs per optical link.

7. The CMOS integrated circuit of claim 5 , wherein the complex encoded signal is transmitted across the optical link using dual polarization, and

wherein the CMOS integrated circuit further comprises 4 DACs and 4 ADCs per optical link.

8. The CMOS integrated circuit of claim 5 , wherein the complex encoded signal is transmitted across the optical link using intensity modulated signals such as PAM4, and

wherein the CMOS integrated circuit further comprises 1 DAC and 1 ADC per optical link.

9. The CMOS integrated circuit of claim 1 , further comprising drivers for electrical-to-optical conversion.

10. The CMOS integrated circuit of claim 1 , further comprising a receiver for optical signal detection comprising a Transimpedance Amplifier (TIA).

11. The CMOS integrated circuit of claim 1 , further comprising an optical-to-electrical converter.

12. The CMOS integrated circuit of claim 4 , wherein the logic enables the CMOS integrated circuit to encode the mm Wave transmission using a complex modulation scheme such as QAM,

wherein the encoding comprises an analogue conversion between baseband and mm Wave frequencies, and

wherein the CMOS integrated circuit comprises 2 DACs and 2 ADCs per mm Wave link.

13. The CMOS integrated circuit of claim 4 , wherein a mm Wave signal is dual polarization, and

wherein the CMOS integrated circuit applies two times a number of ADCs or DACs per mm Wave link for dual polarization.

14. The CMOS integrated circuit of claim 4 , further comprising forward error correction logic.

15. The CMOS integrated circuit of claim 5 , wherein multiple optical links use intensity modulated signals, and

wherein the CMOS integrated circuit further comprises a multilevel driver to function as a DAC, and a multilevel slicer enabled to function as an ADC.

16. The CMOS integrated circuit of claim 1 , wherein the logic enables the CMOS integrated circuit to cause the single data stream to be transmitted over two media to create redundancy in the transmitted encoded single data stream.

17. The CMOS integrated circuit of claim 2 , wherein the logic enables the CMOS integrated circuit to cause the single data stream to be transmitted across different mm Wave bands to allow operation to continue with reduced data rates in an event of link degradation.

18. The CMOS integrated circuit of claim 2 , wherein the logic enables the CMOS integrated circuit to switch the transmission medium during a transmission of the single data stream.

19. The CMOS integrated circuit of claim 15 , wherein the intensity-modulated signals are modulated in a PAM4 encoding.

20. The CMOS integrated circuit of claim 15 , wherein the multiple optical links are provided for redundancy.

21. A CMOS integrated circuit comprising:

digital-to-analogue converters (DACs);

analogue-to-digital converters (ADCs);

a digital signal processor (DSP);

on-chip switching;

an on-chip processor; and

logic enabling the CMOS integrated circuit to:

receive data from one or more transmission media, wherein the transmission media are digital or analog transmission media;

determine a mapping of the data received from the one or more transmission media according to one or more output transmission media, wherein the one or more output transmission media are digital transmission media or analog transmission media;

transform the data received from the one or more transmission media according to the mapping for the one or more output transmission media; and

cause the data to be transmitted by the one or more output transmission media, wherein the one or more transmission media is chosen from the group consisting of an optical link, an electrical link, a mm Wave link, a radio link, and a SERDES link.