Via-first process for connecting a contact and a gate electrode

1. A method for forming an integrated circuit (IC) comprising:

forming an active region (AR) contact extending through a first interlayer dielectric (ILD) layer to an AR of a semiconductor device;

depositing an etch stop layer (ESL) and a second ILD layer covering the first ILD layer and the AR contact, wherein the ESL is between the first and second ILD layers;

performing a first etch into the ESL and the first and second ILD layers to form a first opening exposing a gate electrode of the semiconductor device;

performing a second etch that is into the second ILD layer, and that stops on the ESL, to form a second opening overlying the AR contact and overlapping with the first opening;

performing a third etch into the ESL through the second opening to expose the AR contact, wherein the third etch slants a bottom of the second opening downward from the AR contact to the first opening; and

forming a gate-to-contact (GC) structure filling the first and second openings and electrically coupling the gate electrode to the AR contact.

2. The method according to claim 1 , further comprising:

performing a cleaning process between the performing of the third etch and the forming of the GC structure, wherein the cleaning process further slants the bottom of the second opening downward from the AR contact to the first opening.

3. The method according to claim 1 , wherein the performing of the third etch comprises:

forming plasma from a mixture of hydrogen gas and tetrafluoromethane gas; and

applying the plasma to the ESL.

4. The method according to claim 3 , wherein the hydrogen gas has a first flow rate during the third etch, wherein the tetrafluoromethane gas has a second flow rate during the third etch, and wherein the first flow rate is about 10 times greater than the second flow rate.

5. The method according to claim 1 , wherein the forming of the GC structure comprises:

depositing a barrier layer lining and partially filling the first and second openings;

depositing a plug layer filling a remainder of the first and second openings over the barrier layer; and

performing a planarization into the barrier layer and the plug layer until top surfaces respectively of the barrier layer and the plug layer are about even with a top surface of the second ILD layer.

6. The method according to claim 1 , wherein the forming of the GC structure comprises:

selectively growing a plug layer filling the first and second openings from seed material of the gate electrode and seed material of the AR contact, wherein the plug layer directly contacts sidewalls of the second ILD layer in the first and second openings; and

performing a planarization into the plug layer to level a top surface of the plug layer with a top surface of the second ILD layer.

7. The method according to claim 1 , wherein the third etch extends into the first ILD layer to a depth less than about 10 nanometers on an opposite side of the AR contact as the second opening.

8. A method for forming an integrated circuit (IC) comprising:

forming a gate electrode overlying a substrate;

forming a source/drain region inset into the substrate and bordering to the gate electrode;

forming a conductive contact overlying the source/drain region;

depositing a dielectric film covering the conductive contact and the gate electrode;

patterning the dielectric film to form an opening that overlies the conductive contact and the gate electrode, exposes the gate electrode, and is spaced from the conductive contact;

after the patterning, performing an etch into the dielectric film to extend the opening to the conductive contact; and

forming a conductive structure filling the opening, wherein the conductive structure extends from the conductive contact to the gate electrode.

9. The method according to claim 8 , wherein the dielectric film comprises an etch stop layer (ESL) and an interlayer dielectric (ILD) layer overlying the ESL, wherein the opening is inset into the ESL and the ILD layer, and is spaced from the conductive contact, upon completion of the patterning.

10. The method according to claim 8 , wherein the patterning comprises:

performing a second etch and a third etch to respectively form a vertical segment of the opening and a horizontal segment of the opening, wherein the horizontal segment overlies the conductive contact and the gate electrode, and wherein the vertical segment extends from the horizontal segment to the gate electrode.

11. The method according to claim 8 , wherein the opening shares a common depth at a first location directly over the conductive contact and a second location directly over the gate electrode before the etch, and wherein the opening has a greater depth at the second location than at the first location upon completion of the etch.

12. The method according to claim 8 , wherein a top surface of the conductive contact has a planar profile before the etch, and wherein the top surface of the conductive contact has a curved profile upon completion of the etch.

13. The method according to claim 8 , further comprising:

forming a second source/drain region inset into the substrate and bordering to the gate electrode; and

forming a second conductive contact overlying the second source/drain region;

wherein a top surface of the conductive contact is level with a top surface of the second conductive contact before the etch, and wherein the top surface of the conductive contact is recessed relative to the top surface of the second conductive contact upon completion of the etch.

14. The method according to claim 8 , wherein the conductive contact is level with the gate electrode and has a height greater than that of the gate electrode.

15. A method for forming an integrated circuit (IC) comprising:

forming a gate electrode overlying a substrate;

depositing a first dielectric layer covering the gate electrode;

forming a conductive plug extending through the first dielectric layer and bordering the gate electrode, wherein the conductive plug has a bottom surface recessed relative to a top surface of the gate electrode;

depositing a second dielectric layer covering the conductive plug and the gate electrode;

patterning the first and second dielectric layers to form an opening overlying and exposing the gate electrode, wherein the first dielectric layer has a top surface portion that is between the conductive plug and the opening and that extends substantially in parallel with a top surface of the conductive plug;

performing an etch into the first and second dielectric layers to slant the top surface portion of the first dielectric layer downward away from the conductive plug; and

filling the opening with conductive material to electrically couple the conductive plug to the gate electrode.

16. The method according to claim 15 , wherein a portion of the opening overlies the top surface portion upon completion of the patterning.

17. The method according to claim 15 , wherein the conductive plug and the gate electrode are laterally spaced from each other in a first direction, and wherein a dimension of the gate electrode laterally in a second direction orthogonal to the first direction is greater than that of the opening.

18. The method according to claim 15 , further comprising:

depositing an etch stop layer (ESL) covering the first dielectric layer, wherein the ESL directly contacts the top surface portion, and wherein the second dielectric layer covers the ESL.

19. The method according to claim 15 , wherein the conductive material directly contacts the top surface portion of the first dielectric layer, the top surface of the conductive plug, and the top surface of the gate electrode.

20. The method according to claim 15 , wherein the filling comprises growing the conductive material selectively outward from the top surface of the gate electrode and the top surface of the conductive plug.