Reducing power consumption by preventing memory image destaging to a nonvolatile memory device

1. A system comprising:

a processor; and

a memory including instructions that are executable by the processor for causing the processor to:

determine, subsequent to a computing device being in a first power mode and having a memory image stored in a first nonvolatile memory device that performs a caching function, that the computing device is in a second power mode that is a higher power mode than the first power mode;

in response to determining that the computing device is in the second power mode, generate a first command to store the memory image in a volatile memory device and prevent the memory image from being stored in a second nonvolatile memory device; and

in response to generating the first command, store the memory image in the volatile memory device and remove the memory image from the first nonvolatile memory device in response to the memory image being stored in the volatile memory device.

2. The system of claim 1 , wherein the memory further includes instructions that are executable by the processor for causing the processor to, prior to determining the computing device is in the second power mode:

determine the computing device is in the first power mode; and

in response to determining that the computing device is in the first power mode, generate a second command to store the memory image in the first nonvolatile memory device, the first command preventing the memory image from being stored in the second nonvolatile memory device.

3. The system of claim 1 , wherein the memory further includes instructions that are executable by the processor for causing the processor to prevent the memory image from being stored in the second nonvolatile memory device by allocating a virtual address of the second nonvolatile memory device for storing the memory image, the second nonvolatile memory device excluding the virtual address.

4. The system of claim 1 , wherein the memory further includes instructions that are executable by the processor for causing the processor to, subsequent to storing the memory image in the volatile memory device:

receive a write request for a data unit;

in response to receiving the write request, store the data unit in the first nonvolatile memory device; and

subsequent to a predetermined length of time passing, store the data unit in the second nonvolatile memory device.

5. The system of claim 1 , wherein the computing device comprises a storage device including the first nonvolatile memory device and the second nonvolatile memory device.

6. The system of claim 1 , wherein the first nonvolatile memory device comprises a storage class memory and the second nonvolatile memory device comprises a solid-state drive.

7. A method comprising:

determining, subsequent to a computing device being in a first power mode and having a memory image stored in a first nonvolatile memory device that performs a caching function, that the computing device is in a second power mode that is a higher power mode than the first power mode;

in response to determining that the computing device is in the second power mode, generating a first command to store the memory image in a volatile memory device and prevent the memory image from being stored in a second nonvolatile memory device; and

in response to generating the first command, storing the memory image in the volatile memory device and removing the memory image from the first nonvolatile memory device in response to the memory image being stored in the volatile memory device.

8. The method of claim 7 , further comprising, prior to determining the computing device is in the second power mode:

determine the computing device is in the first power mode; and

in response to determining that the computing device is in the first power mode, generate a second command to store the memory image in the first nonvolatile memory device, the first command preventing the memory image from being stored in the second nonvolatile memory device.

9. The method of claim 7 , further comprising:

preventing the memory image from being stored in the second nonvolatile memory device by allocating a virtual address of the second nonvolatile memory device for storing the memory image, the second nonvolatile memory device excluding the virtual address.

10. The method of claim 7 , further comprising, subsequent to storing the memory image in the volatile memory device:

receive a write request for a data unit;

in response to receiving the write request, store the data unit in the first nonvolatile memory device; and

subsequent to a predetermined length of time passing, store the data unit in the second nonvolatile memory device.

11. The method of claim 7 , wherein the computing device comprises a storage device including the first nonvolatile memory device and the second nonvolatile memory device.

12. The method of claim 7 , wherein the first nonvolatile memory device comprises a storage class memory and the second nonvolatile memory device comprises a solid-state drive.

13. A non-transitory computer-readable medium comprising program code that is executable by a processor for causing the processor to:

determine, subsequent to a computing device being in a first power mode and having a memory image stored in a first nonvolatile memory device that performs a caching function, that the computing device is in a second power mode that is a higher power mode than the first power mode;

in response to determining that the computing device is in the second power mode, generate a first command to store the memory image in a volatile memory device and prevent the memory image from being stored in a second nonvolatile memory device; and

in response to generating the first command, store the memory image in the volatile memory device and remove the memory image from the first nonvolatile memory device in response to the memory image being stored in the volatile memory device.

14. The non-transitory computer-readable medium of claim 13 , further comprising program code that is executable by the processor for causing the processor to, prior to determining the computing device is in the second power mode:

determine the computing device is in the first power mode; and

in response to determining that the computing device is in the first power mode, generate a second command to store the memory image in the first nonvolatile memory device, the first command preventing the memory image from being stored in the second nonvolatile memory device.

15. The non-transitory computer-readable medium of claim 13 , further comprising program code that is executable by the processor for causing the processor to prevent the memory image from being stored in the second nonvolatile memory device by allocating a virtual address of the second nonvolatile memory device for storing the memory image, the second nonvolatile memory device excluding the virtual address.

16. The non-transitory computer-readable medium of claim 13 , further comprising program code that is executable by the processor for causing the processor to, subsequent to storing the memory image in the volatile memory device:

receive a write request for a data unit;

in response to receiving the write request, store the data unit in the first nonvolatile memory device; and

subsequent to a predetermined length of time passing, store the data unit in the second nonvolatile memory device.

17. The non-transitory computer-readable medium of claim 13 , wherein the first nonvolatile memory device comprises a storage class memory and the second nonvolatile memory device comprises a solid-state drive.