Deadtime optimization for GaN half-bridge and full-bridge switch topologies

1. A method of controlling deadtime for a half-bridge or full-bridge switch topology comprising a driver, wherein high side and low side switches comprise GaN transistors, comprising:

receiving a first input comprising a low-side drain current signal I D ;

receiving a second input indicative of a bulk voltage V dc ;

generating a current difference signal I D −1 LOAD , where I LOAD is a load current;

integrating the current difference signal I D −1 LOAD over a time interval of t 2 -t 1 during voltage commutation to generate a current charge output;

∫ t 1 t 2 ( I D ( t )− I LOAD ) dt;

based on the voltage V dc obtaining a reference current charge C oss for the high side switch;

∫ 0 V dc C oss ( V DS ) dV DS 0< V DS <V dc ;t 1 <t<t 2 ;

comparing the current charge output and the reference current charge C oss , and generating a deadtime adjust output signal;

outputting the deadtime adjust signal to the driver.

2. The method of claim 1 , wherein, the deadtime adjust signal is used to reduce or optimize deadtime to reduce deadtime losses, while avoiding cross-conduction.

3. A circuit for controlling deadtime for a half-bridge or full-bridge switch topology comprising a driver, wherein high-side and low-side switches comprise GaN transistors, the circuit comprising a drain current bump filter for generating a current charge output; and circuit elements for comparing the current charge output to a reference current charge C oss and generating a deadtime adjust signal.

4. A circuit for controlling deadtime for a half-bridge or full-bridge switch topology wherein high-side and low-side switches comprise GaN transistors, comprising:

an input for receiving a low-side drain current I D ;

an input for sensing a bulk voltage V dc ;

a unit for generating a current difference signal I D −1 LOAD , where I LOAD is a load current;

a timer for recording and counting the deadtime;

an integrator for integrating the current difference signal I D −1 LOAD over a time interval of t 2 -t 1 during voltage commutation to generate a current charge output;

∫ t 1 t 2 ( I D ( t )− I LOAD ) dt;

a reference source for obtaining a reference current charge C oss based on V dc ;

deadtime adjustment circuitry for receiving the current charge output from the integrator,

comparing the current charge output with the reference current charge C oss , and generating a deadtime adjust signal;

an output for outputting the deadtime adjust signal to the driver.

5. The circuit of claim 4 , wherein the unit for generating a current difference signal I D −I LOAD is a DC blocking unit or a subtractor.

6. The circuit of claim 4 , wherein the integrator is an analog integrator or a digital integrator.

7. The circuit of claim 4 , wherein, based on the sensed bulk voltage V dc , the reference source provides any one of:

real-time calculation of the reference current charge C oss ;

real-time adjustment of a stored reference current charge C oss ;

an offline look-up from a table of reference current charge values.

8. The circuit of claim 4 , wherein:

the unit for generating a current difference signal I D −I LOAD is a DC blocking unit or a subtractor;

the integrator is an analog integrator or a digital integrator; and

based on the sensed bulk voltage V dc the reference source provides any one of:

real-time calculation of the reference current charge C oss ;

real-time adjustment of a stored reference current charge C oss ; and

an offline look-up from a table of reference current charge values.

9. A power switching system comprising a GaN half-bridge or a GaN full-bridge and a deadtime optimization system comprising a drain current bump filter for generating a current charge output during voltage commutation; and circuit elements for comparing the current charge output to a reference current charge C oss , and generating a deadtime adjust signal.