IP Library › Granted Patent US 12,373,687
Granted Patent B2
US 12,373,687 · App. 17/537,156 · Granted Jul 29, 2025

Machine learning model training using an analog processor

Inventors: Darius Bunandar (Boston, MA); Ludmila Levkova (Chevy Chase, MD); Nicholas Dronen (Newton, MA); Lakshmi Nair (Somerville, MA); David Widemann (Danville, CA); David Walter (Boston, MA); Martin B. Z. Forsythe (Jamaica Plain, MA); Tomo Lazovich (Cambridge, MA); Ayon Basumallik (Framingham, MA); Nicholas C. Harris (Boston, MA)
Assignee: Lightmatter, Inc.
G06N3/08G06F7/4876G06N3/065
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Quick Facts
Patent No.
US 12,373,687
App. No.
17/537,156
Granted
Jul 29, 2025
Kind
B2
Abstract

Described herein are techniques of training a machine learning model and performing inference using an analog processor. Some embodiments mitigate the loss in performance of a machine learning model resulting from a lower precision of an analog processor by using an adaptive block floating-point representation of numbers for the analog processor. Some embodiments mitigate the loss in performance of a machine learning model due to noise that is present when using an analog processor. The techniques involve training the machine learning model such that it is robust to noise.

Claims (78)

1. A system comprising:

circuitry comprising an analog processor;

wherein the circuitry is configured to train a machine learning model, the training comprising performing one or more matrix operations to learn parameters of the machine learning model using the analog processor, wherein performing a matrix operation of the one or more matrix operations to learn the parameters of the machine learning model using the analog processor comprises:

determining a scaling factor for a first portion of a first matrix involved in the matrix operation;

scaling the first portion of the first matrix using the scaling factor for the first portion of the first matrix to obtain a scaled first portion of the first matrix;

programming the analog processor using the scaled first portion of the first matrix;

performing, by the analog processor programmed using the scaled first portion of the first matrix, the matrix operation to generate a first output; and

determining a result of the matrix operation using the first output generated by the analog processor.

2. The system of claim 1 , wherein performing the matrix operation further comprises:

determining a scaling factor for a first portion of a second matrix involved in the matrix operation;

scaling the first portion of the second matrix using the scaling factor for the first portion of the second matrix to obtain a scaled first portion of the second matrix;

programming the analog processor using the scaled first portion of the second matrix; and

performing, by the analog processor programmed using the scaled first portion of the second matrix, the matrix operation to generate the first output.

3. The system of claim 1 , wherein performing the one or more matrix operations to learn the parameters of the machine learning model using the analog processor comprises:

determining a scaling factor for a second portion of the first matrix;

scaling the second portion of the first matrix using the scaling factor for the second portion of the first matrix to obtain a scaled second portion of the first matrix;

programming the analog processor using the scaled second portion of the first matrix;

performing, by the analog processor programmed using the scaled second portion of the first matrix, the matrix operation to generate a second output; and

determining the result of the matrix operation using the second output generated by the analog processor.

4. The system of claim 3 , wherein the first scaling factor is different from the second scaling factor.

5. The system of claim 1 , wherein the first portion of the first matrix is a first vector of the first matrix.

6. The system of claim 1 , wherein determining the result of the matrix operation using the first output generated by the analog processor comprises:

determining an output scaling factor for the first output generated by the analog processor using the first scaling factor;

scaling the first output using the output scaling factor to obtain a scaled first output; and

determining the result of the matrix operation using the scaled first output.

7. The system of claim 1 , wherein:

determining the first scaling factor for the first portion of the first matrix comprises determining a maximum absolute value of the first portion of the first matrix; and

scaling the first portion of the first matrix using the first scaling factor comprises scaling values of the first portion of the first matrix using the maximum absolute value of the first portion of the first matrix.

8. The system of claim 1 , wherein:

the analog processor is configured to operate using a fixed-point representation of values; and

programming the analog processor using the scaling of the first portion of the first matrix comprises converting values of the scaled first portion of the first matrix into the fixed-point representation.

9. The system of claim 8 , wherein:

the circuitry further comprises a digital controller configured to operate using a floating-point representation of values; and

a dynamic range of the floating-point representation is greater than a dynamic range of the fixed-point representation.

10. The system of claim 1 , wherein performing the one or more matrix operations to learn parameters of the machine learning model using the analog processor comprises amplifying or attenuating at least one analog signal used to perform a matrix operation of the one or more matrix operations.

11. The system of claim 10 , wherein amplifying or attenuating the at least one analog signal used to perform the matrix operation comprises:

distributing a zero pad among different portions of a matrix involved in the matrix operation; and

programming of the analog processor using the matrix with the zero pad distributed among different portions of the matrix.

12. The system of claim 1 , wherein performing the one or more matrix operations comprises performing the one or more matrix operations between a matrix of parameters of the machine learning model and a matrix of inputs to the machine learning model.

13. The system of claim 1 , wherein performing the one or more matrix operations to learn the parameters of the machine learning model using the analog processor comprises performing the one or more matrix operations to determine outputs of the machine learning model for a set of inputs.

14. The system of claim 1 , wherein performing the one or more matrix operations to learn the parameters of the machine learning model using the analog processor further comprises:

performing the one or more matrix operations using the analog processor to determine a gradient of a loss function; and

updating parameters of the machine learning model using the gradient of the loss function.

15. The system of claim 1 , wherein the training comprises performing a plurality of iterations, wherein performing each of at least some of the plurality of iterations comprises:

determining updated parameters of the machine learning model; and

setting parameters of the machine learning model to an average of the updated parameters and parameters set at one or more previous iterations of the plurality of iterations.

16. The system of claim 1 , wherein the matrix operation is a matrix multiplication.

17. The system of claim 1 , wherein the analog processor is a photonic processor, wherein performing the one or more matrix operations to learn the parameters of the machine learning model using the analog processor comprises processing light using the photonic processor.

18. The system of claim 1 , wherein the circuitry further comprises a digital controller.

19. The system of claim 1 , wherein the machine learning model is a neural network.

20. A system comprising:

circuitry comprising an analog processor;

wherein the circuitry is configured to train a machine learning model, the training comprising performing one or more matrix operations to learn parameters of the machine learning model using the analog processor, wherein performing the one or more matrix operations to learn parameters of the machine learning model using the analog processor comprises amplifying or attenuating at least one analog signal used to perform a matrix operation of the one or more matrix operations, wherein amplifying or attenuating the at least one analog signal used to perform the matrix operation comprises:

programming the analog processor using multiple copies of a matrix involved in the matrix operation.

21. The system of claim 20 , wherein performing the one or more matrix operations comprises performing the one or more matrix operations between a matrix of parameters of the machine learning model and a matrix of inputs to the machine learning model.

22. The system of claim 20 , wherein performing the one or more matrix operations to learn the parameters of the machine learning model using the analog processor comprises performing the one or more matrix operations to determine outputs of the machine learning model for a set of inputs.

23. The system of claim 20 , wherein performing the one or more matrix operations to learn the parameters of the machine learning model using the analog processor further comprises:

performing the one or more matrix operations using the analog processor to determine a gradient of a loss function; and

updating parameters of the machine learning model using the gradient of the loss function.

24. A method comprising:

training a machine learning model using a system comprising an analog processor, the training comprising performing one or more matrix operations to learn parameters of the machine learning model using the analog processor, wherein performing a matrix operation of the one or more matrix operations to learn the parameters of the machine learning model using the analog processor comprises:

determining a scaling factor for a first portion of a first matrix involved in the matrix operation;

scaling the first portion of the first matrix using the scaling factor for the first portion of the first matrix to obtain a scaled first portion of the first matrix;

programming the analog processor using the scaled first portion of the first matrix;

performing, by the analog processor programmed using the scaled first portion of the first matrix, the matrix operation to generate a first output; and

determining a result of the matrix operation using the first output generated by the analog processor.

25. The method of claim 24 , wherein performing the matrix operation further comprises:

determining a scaling factor for a first portion of a second matrix involved in the matrix operation;

scaling the first portion of the second matrix using the scaling factor for the first portion of the second matrix to obtain a scaled first portion of the second matrix;

programming the analog processor using the scaled first portion of the second matrix; and

performing, by the analog processor programmed using the scaled first portion of the second matrix, the matrix operation to generate the first output.

26. A non-transitory computer-readable storage medium storing instructions that, when executed by circuitry including an analog processor, cause circuitry to perform:

training a machine learning model, the training comprising performing one or more matrix operations to learn parameters of the machine learning model using the analog processor, wherein performing a matrix operation of the one or more matrix operations to learn the parameters of the machine learning model using the analog processor comprises:

determining a scaling factor for a first portion of a first matrix involved in the matrix operation;

scaling the first portion of the first matrix using the scaling factor for the first portion of the first matrix to obtain a scaled first portion of the first matrix;

programming the analog processor using the scaled first portion of the first matrix;

performing, by the analog processor programmed using the scaled first portion of the first matrix, the matrix operation to generate a first output; and

determining a result of the matrix operation using the first output generated by the analog processor.

Assignments (4)
TERMINATION OF IP SECURITY AGREEMENT Recorded Nov 5, 2024
From: EASTWARD FUND MANAGEMENT, LLC
To: LIGHTMATTER, INC.
Reel/Frame 069304/0700 →
RELEASE OF SECURITY INTEREST Recorded Mar 31, 2023
From: EASTWARD FUND MANAGEMENT, LLC
To: LIGHTMATTER, INC.
Reel/Frame 063209/0966 →
SECURITY INTEREST Recorded Dec 27, 2022
From: LIGHTMATTER, INC.
To: EASTWARD FUND MANAGEMENT, LLC
Reel/Frame 062230/0361 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2022
From: BUNANDAR, DARIUS; LEVKOVA, LUDMILA; DRONEN, NICHOLAS; NAIR, LAKSHMI; WIDEMANN, DAVID; WALTER, DAVID; FORSYTHE, MARTIN B.Z.; LAZOVICH, TOMO; BASUMALLIK, AYON; HARRIS, NICHOLAS C.
To: LIGHTMATTER, INC.
Reel/Frame 059145/0317 →
Continuity (3)
Provisional Application 63160592 · Mar 12, 2021
Provisional Application 63119472 · Nov 30, 2020
Related Publication 20220172052A1 · Jun 2, 2022
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