Debug trace of cache memory requests

1. An apparatus, comprising:

a plurality of processor circuits;

a cache memory circuit; and

a trace control circuit configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to:

monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit;

select a particular memory request of monitored memory requests using an arbitration algorithm;

allocate space in a trace buffer to the particular memory request; and

store, in the trace buffer, information associated with the particular memory request.

2. The apparatus of claim 1 , wherein the particular memory request is a read request that results in a cache miss.

3. The apparatus of claim 2 , wherein to store the associated information in the trace buffer, the trace control circuit is configured to copy cache fill data enroute to the cache memory circuit.

4. The apparatus of claim 1 , wherein the trace control circuit is further configured to:

store the particular memory request in an entry in a request buffer; and

delete the entry in response to a determination that the information associated with the particular memory request has been stored in the trace buffer.

5. The apparatus of claim 1 , wherein the trace control circuit is further configured to, in response to a determination that the trace buffer has reached a threshold level of capacity, issue a stall request to one or more of the processor circuits.

6. The apparatus of claim 1 , further comprising a fill buffer, and wherein the trace control circuit is further configured to store the associated information in the fill buffer in response to a determination that the trace buffer does not have sufficient space for the associated information.

7. The apparatus of claim 1 , wherein the trace control circuit is further configured to include a timestamp with the associated information.

8. A method, comprising:

in response to an activation of a mode to record information indicative of program execution of one or more processor circuits, monitoring, by a trace control circuit, memory requests issued from the one or more processor circuits;

determining, by the trace control circuit, that a subset of the issued memory requests will cause a cache memory circuit to fetch data from a different memory circuit;

selecting, by the trace control circuit, a particular memory request of the subset of the issued memory requests using an arbitration algorithm;

allocating, by the trace control circuit, locations in a trace buffer for the particular memory request; and

storing, by the trace control circuit in the locations in the trace buffer, information associated with processing of the particular memory request.

9. The method of claim 8 , further comprising selecting the particular memory request in response to determining that the particular memory request is a read request that results in a cache miss.

10. The method of claim 9 , further comprising, prior to the storing, reading cache fill data associated with the particular memory request as the cache fill data is enroute to the cache memory circuit.

11. The method of claim 8 , further comprising:

storing the subset of the issued memory requests in respective entries in a request buffer; and

deleting a respective entry in response to determining that information associated with a corresponding memory request has been stored in the trace buffer.

12. The method of claim 8 , further comprising, in response to an indication that the trace buffer has reached a threshold capacity, stalling at least one of the one or more processor circuits.

13. The method of claim 12 , further comprising, in response to the indication, storing the associated information in a fill buffer.

14. The method of claim 8 , further comprising including a timestamp with the associated information.

15. A system, comprising:

a memory circuit;

a cache memory circuit configured to issue memory requests to the memory circuit in response to a cache miss;

a trace control circuit configured, in response to activation of a mode to record information associated with accesses to the memory circuit, to:

determine that the cache memory circuit issued one or more memory requests to the memory circuit;

select a particular memory request of the one or more memory requests using an arbitration algorithm;

allocate locations in a trace buffer for the particular memory request; and

store, in the locations in the trace buffer, information associated with processing of the particular memory request.

16. The system of claim 15 , wherein to select the particular memory request, the trace control circuit is further configured to select the particular memory request in response to a determination that the particular memory request is a read request that results in the cache miss.

17. The system of claim 16 , wherein the trace control circuit is further configured, prior to the storing, to read cache fill data associated with the particular memory request as the cache fill data is in transit to the cache memory circuit.

18. The system of claim 15 , wherein the trace control circuit is further configured to:

store the one or more memory requests in respective entries in a request buffer; and

delete a respective entry in response to a determination that information associated with a corresponding memory request has been stored in the trace buffer.

19. The system of claim 15 , wherein the trace control circuit is further configured, in response to a determination that the trace buffer does not have sufficient space to hold the associated information, to assert a stall signal, wherein the stall signal causes the cache memory circuit to cease issuing further memory requests.

20. The system of claim 19 , wherein the trace control circuit is further configured to store the associated information in a fill buffer in response to the determination that the trace buffer does not have sufficient space.