Vertical 3D single word line gain cell with shared read/write bit line
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.
1. A method of forming multiple levels of two-transistor (2T) memory cells, the method comprising:
forming, vertically on a substrate, multiple levels of a sacrificial material alternated with multiple levels of a dielectric material;
forming first openings in the multiple levels of the dielectric material and forming multiple levels of recesses in the multiple levels of the sacrificial material;
forming multiple levels of channel regions for write transistors and charge storage transistors of the 2T memory cells, wherein a channel region of a write transistor contacts a charge storage structure of a charge storage transistor in each 2T memory cell;
forming second vertical openings in the multiple levels of the dielectric material and the multiple levels of the channel regions, and filling the second vertical openings with the sacrificial material;
forming gate regions of the write transistors and the charge storage transistors of the 2T memory cells;
forming multiple vertically extending access lines, each access line to control gate regions of both a charge storage transistor and a write transistor of a 2T memory cell in multiple respective levels of the 2T memory cells; and
removing the sacrificial material and forming bit line pairs for the 2T memory cells using the second vertical openings, wherein only one bit line pair contacts one 2T memory cell.
2. The method of claim 1 , wherein the forming multiple levels of channel regions includes disposing a polysilicon film on two sides of a recess to form a two-sided read channel region of a charge storage transistor.
3. The method of claim 2 , wherein the forming multiple levels of floating gate structures of the 2T memory cells includes disposing gate oxide between sides of the two-sided read channel region of the charge storage transistor.
4. The method of claim 3 , wherein the forming multiple levels of channel regions includes disposing gallium phosphide between the sides of the two-sided channel region of the charge storage transistor and in contact with the charge storage structure to form a write channel region of a write transistor.
5. The method of claim 2 , wherein the forming bit line pairs for the 2T memory cells includes:
removing the sacrificial material from a second vertical opening to expose a first end of the two-sided channel region;
disposing a conductive material in the second vertical opening to form a first bit line of a bit line pair of a 2T memory cell, wherein the first bit line contacts the first end of the two-sided channel region;
forming an opening to expose a second end of the two-sided channel region; and
disposing the conductive material to form the second bit line of the bit line pair of the 2T memory cell, wherein the second bit line contacts the second end of the two-sided channel region.
6. The method of claim 1 , wherein the forming bit line pairs for the 2T memory cells includes:
filling the second vertical openings with a conductive material to form first bit lines of the bit line pairs;
etching the conductive material to separate the formed first bit lines; and
filling the opening with an insulating oxide to electrically isolate the formed first bit lines.
7. The method of claim 1 ,
including forming multiple levels of floating gate structures for the charge storage transistors, and
wherein the forming gate regions of the charge storage transistors includes disposing gate oxide to form control gate regions of the charge storage transistors.
8. The method of claim 7 , wherein the forming vertically extending access lines includes forming, for a same single access line, contacts to a gate region of a write transistor and a control gate region of a charge storage transistor of a 2T memory cell.
9. The method of claim 1 , wherein the forming multiple vertically extending access lines includes forming contacts for a single vertically extending access line to gate regions of a write transistor and a gate region of a charge storage transistor of a 2T memory cell of a first level of the 2T memory cells, and to gate regions of a write transistor and a charge storage transistor of a 2T memory cell of a second level of the 2T memory cells.