AUTO-ENUMERATION OF PERIPHERAL DEVICES ON A SERIAL COMMUNICATION BUS
Each device on a bus auto-enumerates at power up or reset to assign a unique address to the device based on the resistance value of an external resistor. A current source supplies a current to a terminal to which a resistor is coupled. Each device has a resistor attached with a different resistance value. Each device senses the voltage at the terminal and the voltage corresponds to the unique device address on the bus. Following enumeration, the devices on the bus are individually addressable using their unique address.
1 . A peripheral device comprising:
a terminal;
a current source coupled to provide a current to the terminal; and
an address register to store an address corresponding to a voltage on the terminal, the address to identify the peripheral device on a bus.
2 . The peripheral device as recited in claim 1 further comprising an analog to digital converter to convert the voltage on the terminal to a digital value indicative of the address.
3 . The peripheral device as recited in claim 1 wherein the peripheral device responds to a command on the bus containing the address in an address field of the command in accordance with the command.
4 . The peripheral device as recited in claim 1 wherein the address is stored in the address register responsive to a power on condition.
5 . The peripheral device as recited in claim 1 wherein the address is stored in the address register responsive to reset.
6 . The peripheral device as recited in claim 1 wherein the terminal is used as an output terminal during operation of the peripheral device after the address is determined.
7 . The peripheral device as recited in claim 1 wherein the voltage is determined according to the current provided to the terminal and a resistance coupled to the terminal.
8 . The peripheral device as recited in claim 1 further comprising a communication interface coupled to the bus, the communication interface including, a clock terminal, a serial data in terminal, a serial data out terminal, and a chip select terminal.
9 . A system for auto-enumeration of devices on a bus comprising:
a plurality of devices coupled to the bus;
a first device of the plurality of devices including a first terminal, a first current source coupled to provide a first current to the first terminal, and a first address register to store a first address corresponding to a first voltage on the first terminal; and
a second device of the plurality of devices including a second terminal, a second current source coupled to provide a second current to the second terminal, and a second address register to store a second address corresponding to a second voltage on the second terminal.
10 . The communication system as recited in claim 9 further comprising a plurality of resistors coupled respectively to the plurality of devices, a first resistor of the plurality of resistors is coupled to the first terminal and a second terminal of the plurality of resistors is coupled to the second terminal.
11 . The communication system as recited in claim 10 wherein the first device is responsive to a command on the bus containing the first address and the second device is responsive to a second command on the bus containing the second address.
12 . The communication system as recited in claim 10 wherein the plurality of devices includes six devices including the first device and the second device, and each of respective voltages on respective terminals of the plurality of devices have a different voltage and nominal values of the respective voltages are linearly spaced.
13 . The communication system as recited in claim 10 wherein the plurality of devices includes six devices including the first device and the second device, and each of respective voltages on respective terminals of the plurality of devices have a different voltage and wherein nominal values of the respective voltages are non-linearly spaced.
14 . The communication system as recited in claim 9 wherein the first device and the second device store the first address and the second address, respectively, in the first address register and the second address register responsive to a power on condition.
15 . The communication system as recited in claim 9 wherein the first device and the second device store the first address and the second address, respectively, in the first address register and the second address register responsive to a reset.
16 . The communication system as recited in claim 9 wherein the first terminal is used as an output terminal following determination of the first address.
17 . The communication system as recited in claim 9 wherein each of the plurality of peripheral devices comprises a communication interface coupled to the bus and the communication interface includes a clock terminal, a serial data in terminal, a serial data out terminal, and a chip select terminal.
18 . A method for determining an address of a device on a bus comprising:
supplying a terminal of the device with a current from a current source on the device;
determining a voltage on the terminal; and
storing an address corresponding to the voltage in address register of the device.
19 . The method as recited in claim 18 further comprising converting the voltage to a digital value in an analog to digital converter.
20 . The method as recited in claim 18 further comprising the device responding to a command on the bus containing the address in an address field of the command.
21 . The method as recited in claim 18 further comprising storing the address in the address register responsive to a power on condition.
22 . The method as recited in claim 18 further comprising storing the address in the address register responsive to reset.
23 . The method as recited in claim 18 further comprising using the terminal as an output terminal during operation of the peripheral device after a power on condition.
24 . The method as recited in claim 18 further comprising generating the voltage according to the current and a resistance of a resistor coupled to the terminal.