Deterministic replay of a multi-threaded trace on a multi-threaded processor
A deterministic replay of a multi-threaded trace on a multi-threaded processor is described. An example of a computer-readable storage medium includes instructions to cause at least one processor to receive graphics processing unit (GPU) program code for tracing, the program code including a plurality of instructions; analyze the plurality of instructions to identify instructions of the program code that are events requiring synchronization; instrument each of the identified events to generate instrumented program code; execute the instrumented program code on a plurality of hardware threads of the GPU to generate trace data; and emulate the trace data utilizing an emulator on a plurality of hardware traces of a central processing unit (CPU), including replaying the identified events according to an order of occurrence of the identified events.
1. At least one non-transitory computer-readable storage medium comprising instructions for execution by at least one processor that, when executed, cause the at least one processor to:
receive graphics processing unit (GPU) program code for tracing, the program code including a plurality of instructions;
analyze the plurality of instructions to identify instructions of the program code that are events requiring synchronization;
instrument each of the identified events to generate instrumented program code;
execute the instrumented program code on a plurality of hardware threads of the GPU to generate trace data; and
emulate the trace data utilizing an emulator on a plurality of hardware traces of a central processing unit (CPU), including replaying the identified events according to an order of occurrence of the identified events.
2. The at least one non-transitory computer-readable storage medium of claim 1 , wherein the identified events include one or more of a code dispatch, a code end-of-thread event, a read or write access to global memory, a read or write access to shared local memory, an exit from a waiting state, or a memory fence instruction.
3. The at least non-transitory one computer-readable storage medium of claim 1 , wherein instrumenting each of the identified events includes:
dividing the program code into a sequence of basic blocks; and
inserting a trace instruction into each basic block of the sequence of basic blocks that contains an event.
4. The at least one non-transitory computer-readable storage medium of claim 3 , wherein instrumenting each of the identified events further includes:
inserting a dynamic instruction count relating to an original instruction in each basic block where a tracing instruction is added.
5. The at least one non-transitory computer-readable storage medium of claim 1 , wherein the execution of the program code on the plurality of hardware traces of the GPU includes, upon a hardware trace reaching an identified event in the program code, reserving a next available slot of a trace buffer and storing event data for the event into the reserved slot of the trace buffer.
6. The at least one non-transitory computer-readable storage medium of claim 5 , wherein emulating the trace data includes, for a next instruction that is an identified event to be emulated by a hardware thread of the CPU:
determining whether the identified event is a current event for emulation according to the stored event data in the trace buffer;
if the identified event is the current event for emulation, emulating the instruction on the hardware thread of the CPU; and
if the identified event is not the current event for emulation, switching emulation to another hardware thread of the CPU.
7. The at least one non-transitory computer-readable storage medium of claim 1 , wherein the program code is a kernel or a shader.
8. The at least one non-transitory computer-readable storage medium of claim 1 , wherein the plurality of hardware traces of the GPU is greater in number than the plurality of hardware traces of the CPU.
9. A method comprising:
receiving graphics processing unit (GPU) program code for tracing, the program code including a plurality of instructions;
analyzing the plurality of instructions to identify instructions of the program code that are events requiring synchronization;
instrumenting each of the identified events to generate instrumented program code;
executing the instrumented program code on a plurality of hardware threads of the GPU to generate trace data; and
emulating the trace data utilizing an emulator on a plurality of hardware traces of a central processing unit (CPU), including replaying the identified events according to an order of occurrence of the identified events.
10. The method of claim 9 , wherein the identified events include one or more of a code dispatch, a code end-of-thread event, a read or write access to global memory, a read or write access to shared local memory, an exit from a waiting state, or a memory fence instruction.
11. The method of claim 9 , wherein instrumenting each of the identified events includes:
dividing the program code into a sequence of basic blocks; and
inserting a trace instruction into each basic block of the sequence of basic blocks that contains an event.
12. The method of claim 11 , wherein instrumenting each of the identified events further includes:
inserting a dynamic instruction count relating to an original instruction in each basic block where a tracing instruction is added.
13. The method of claim 9 , wherein the execution of the program code on the plurality of hardware traces of the GPU includes, upon a hardware trace reaching an identified event in the program code, reserving a next available slot of a trace buffer and storing event data for the event into the reserved slot of the trace buffer.
14. The method of claim 13 , wherein emulating the trace data includes, for a next instruction that is an identified event to be emulated by a hardware thread of the CPU:
determining whether the identified event is a current event for emulation according to the stored event data in the trace buffer;
if the identified event is the current event for emulation, emulating the instruction on the hardware thread of the CPU; and
if the identified event is not the current event for emulation, switching emulation to another hardware thread of the CPU.
15. An apparatus comprising:
one or more processors including a central processing unit (CPU) having a plurality of hardware threads and a graphics processing unit (GPU) having a plurality of hardware threads;
a memory for storage of data including program data for tracing;
wherein the one or more processors are to:
receive GPU program code for tracing, the program code including a plurality of instructions;
analyze the plurality of instructions to identify instructions of the program code that are events requiring synchronization;
instrument each of the identified events to generate instrumented program code;
execute the instrumented program code on the plurality of hardware threads of the GPU to generate trace data; and
emulate the trace data utilizing an emulator on the plurality of hardware traces of the CPU, including replaying the identified events according to an order of occurrence of the identified events.
16. The apparatus of claim 15 , wherein instrumenting each of the identified events includes the one or more processors to:
divide the program code into a sequence of basic blocks; and
insert a trace instruction into each basic block of the sequence of basic blocks that contains an event.
17. The apparatus of claim 16 , wherein instrumenting each of the identified events further includes the one or more processors to:
insert a dynamic instruction count relating to an original instruction in each basic block where a tracing instruction is added.
18. The apparatus of claim 15 , wherein the execution of the program code on the plurality of hardware traces of the GPU includes, upon a hardware trace reaching an identified event in the program code, reserving a next available slot of a trace buffer and storing event data for the event into the reserved slot of the trace buffer.
19. The apparatus of claim 18 , wherein emulating the trace data includes, for a next instruction that is an identified event to be emulated by a hardware thread of the CPU, the one or more processors to:
determine whether the identified event is a current event for emulation according to the stored event data in the trace buffer;
if the identified event is the current event for emulation, emulate the instruction on the hardware thread of the CPU; and
if the identified event is not the current event for emulation, switch emulation to another hardware thread of the CPU.
20. The apparatus of claim 15 , wherein the plurality of hardware traces of the GPU is greater in number than the plurality of hardware traces of the CPU.