Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
View Patent ↗Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
1. A method comprising:
reading duty cycle results for a first duty cycle code from a mode register, wherein the duty cycle results indicate a first adjustment; and
writing a second duty cycle code for the duty cycle adjuster to the mode register when the duty cycle results indicate a change associated with the first duty cycle code, wherein the second duty cycle code is associated with a second adjustment.
2. The method of claim 1 , further comprising writing the first duty cycle code to the mode register.
3. The method of claim 1 , wherein the second adjustment has a different size than the first adjustment.
4. The method of claim 3 , wherein the second adjustment is smaller than the first adjustment.
5. The method of claim 1 , wherein the first adjustment increases the duty cycle and the second adjustment decreases the duty cycle.
6. The method of claim 1 , wherein the first adjustment decreases the duty cycle and the second adjustment increases the duty cycle.
7. The method of claim 1 , further comprising writing a value to a second mode register, wherein the first value causes a duty cycle monitor to monitor the duty cycle and generate the duty cycle results.
8. The method of claim 1 , further comprising writing a value to a second mode register, wherein the value causes a duty cycle monitor to stop monitoring the duty cycle.
9. A method comprising:
monitoring a duty cycle of a clock signal;
writing a duty cycle result to a mode register based on the monitoring;
receiving a duty cycle adjuster code; and,
adjusting the duty cycle of the clock signal based on the duty cycle adjuster code.
10. The method of claim 9 , further comprising:
writing a value to a second mode register responsive to a mode register write command, wherein the monitoring is performed responsive to the value.
11. The method of claim 9 , further comprising:
writing a value to a second mode register responsive to a mode register write command; and
ceasing monitoring the duty cycle of the clock signal responsive to the value.
12. The method of claim 9 , further comprising:
monitoring the duty cycle of the clock signal after adjusting the duty cycle;
writing a second duty cycle result to the mode register based on the monitoring;
receiving a second duty cycle adjuster code; and
adjusting the duty cycle of the clock signal based on the second duty cycle adjuster code.
13. The method of claim 12 , wherein the duty cycle is adjusted by, different amounts based on the duty cycle adjuster code and the second duty cycle adjuster code.
14. The method of claim 13 , wherein the duty cycle is adjusted by a greater amount based on the duty cycle adjuster code and by a lesser amount based on the second duty cycle adjuster code.
15. The method of claim 12 , wherein the duty cycle of the clock signal is increased based on the duty cycle adjuster code and decreased based on the second duty cycle adjuster code.
16. The method of claim 12 , wherein the duty cycle of the clock signal is decreased based on the duty cycle adjuster code and increased based on the second duty cycle adjuster code.
17. A method comprising:
issuing a first mode register write command to write a first duty cycle adjuster code associated with a first step size to a first mode register to set a duty cycle adjuster circuit;
issuing a second mode register write command to write a first value to first opcode of a second mode register to start a duty cycle monitor operation;
issuing a third mode register write command to write a second value to the first opcode to stop the first duty cycle monitor operation; and
issuing a first mode register read command to read duty cycle results from the duty cycle monitor operation.
18. The method of claim 17 , further comprising:
comparing the duty cycle results from the duty cycle monitor operation to duty cycle results from a previous duty cycle monitor operation; and
issuing a fourth mode register write command to write a second duty cycle adjuster code to the first mode register to set the duty cycle adjuster circuit, wherein a second step size associated with the second duty cycle adjuster code is based, at least in part, on the comparing.
19. The method of claim 18 , wherein the second step size is different than the first step size when the duty cycle results of the duty cycle monitor operation indicate a duty cycle condition that is opposite of the duty cycle condition indicated by the duty cycle results from the previous duty cycle monitor operation.
20. The method of claim 17 , further comprising issuing a fourth mode register write command to write a third value to a second opcode of the second mode register to flip an input condition for a duty cycle monitor circuit.