Backplane for an array of emissive elements
A plurality of pixel drive circuits form part of an array of emissive elements. The plurality of pixel drive circuits are disposed to form a plurality of rows and a plurality of columns. The plurality of pixel drive circuits are organized into sets of pixel drive circuits, and each set comprises at least one pixel drive circuit. A FET of a set of pixel drive circuits shares a common well with other FETs of similar function in the same set of pixel drive circuits positioned therein, such that the variance of the threshold voltages of those FETs is substantially reduced. Each of the pixel drive circuits comprises a circuit operative to deliver a current at a predetermined voltage to an emissive device and a memory circuit operative to receive modulation data and to use same to modulate the current output of the pixel drive circuit.
1. An apparatus, comprising:
a plurality of pixel drive circuits including a first pixel drive circuit and a second pixel drive circuit, the plurality of pixel drive circuits forming part of an array of emissive elements; and
a first field effect transistor (FET) of the first pixel drive circuit in a first quadrant of a common well sharing the common well with a second FET in the second pixel drive circuit in a second quadrant of the common well such that a variance of a threshold voltage between the first FET and the second FET is substantially reduced,
the first pixel drive circuit including a circuit configured to deliver a current at a predetermined voltage to an emissive device and a memory circuit configured to receive modulation data and to use the modulation data to modulate a current output of the first pixel drive circuit.
2. The apparatus of claim 1 , wherein the common well is shared among a m columns by n rows of the plurality of pixel drive circuits, m comprising an integer greater than one and n comprising an integer equal to or greater than one.
3. The apparatus of claim 2 , wherein a number of the n rows is greater than one.
4. The apparatus of claim 1 , wherein the common well of the plurality of pixel drive circuits is included in a part of at least one row of the plurality of pixel drive circuits.
5. The apparatus of claim 4 , wherein the common well occupies part of at least one row of the plurality of pixel drive circuits is included in a contiguous part of an adjacent row of the plurality of pixel drive circuits.
6. The apparatus of claim 1 , wherein the common well is an n-well and the first FET located therein is a p-channel FET.
7. The apparatus of claim 1 , wherein the common well is a p-well and the first FET located therein is an n-channel FET.
8. The apparatus of claim 1 , wherein the common well is biased to a common supply voltage over a plurality of contacts.
9. An apparatus, comprising:
a plurality of pixel drive circuits organized into sets of pixel drive circuits, each set pixel drive circuits including at least one pixel drive circuit, the plurality of pixel drive circuits defining part of an array of emissive elements and defining a plurality of rows and a plurality of columns; and
a first field effect transistor (FET) of a set of pixel drive circuits sharing a common well with a second FET of similar function to the first FET in the set of pixel drive circuits, the first FET being in a first quadrant of the common well and the second FET being in a second well within the common well such that a variance of a threshold voltage of first FET and a threshold voltage of the second FET is substantially reduced,
each of the set of pixel drive circuits including a circuit configured to deliver a current at a predetermined voltage to an emissive device and a memory circuit configured to receive modulation data and to modulate a current output of each of the set of pixel drive circuits,
the common well being biased to a common supply voltage over a plurality of contacts aligned along a bus.
10. The apparatus of claim 9 , wherein the common well is shared among a m columns by n rows of the set of pixel drive circuits where m is an integer greater than one and n is an integer equal to or greater than one.
11. The apparatus of claim 10 , wherein a number of the n rows is greater than one.
12. The apparatus of claim 9 , wherein the common well of each set of pixel drive circuits is included in a part of at least one row of the plurality of pixel drive circuits.
13. The apparatus of claim 12 , wherein the common well occupies part of at least one row of the plurality of pixel drive circuits is included in a contiguous part of an adjacent row of the plurality of pixel drive circuits.
14. The apparatus of claim 9 , wherein the common well is an n-well and the first FET located therein is a p-channel FET.
15. The apparatus of claim 9 , wherein the common well is a p-well and the first FET located therein is an n-channel FET.
16. The apparatus of claim 9 , wherein the common well is biased to a common supply voltage over a plurality of contacts.
17. An apparatus, comprising:
a plurality of pixel drive circuits including a first pixel drive circuit and a second pixel drive circuit, the plurality of pixel drive circuits forming part of an array of emissive elements; and
a first field effect transistor (FET) of the first pixel drive circuit in a first quadrant of a common well sharing the common well with a second FET in the second pixel drive circuit in a second quadrant of the common well such that the first pixel drive circuit is mirrored with the second pixel drive circuit across an axis,
the first pixel drive circuit including a circuit configured to deliver a current at a predetermined voltage to an emissive device and a memory circuit configured to receive modulation data and to use the modulation data to modulate a current output of the first pixel drive circuit.
18. The apparatus of claim 17 , wherein the common well is biased to a common supply voltage over a plurality of contacts.