Granted Patent B2

US 12,432,785 · App. 17/552,993 · Granted Sep 30, 2025

Inventors: Zoran Utkovski (Berlin, DE); Johannes Dommel (Berlin, DE); Thomas Haustein (Berlin, DE); Lars Thiele (Berlin, DE); Thomas Fehrenbach (Berlin, DE); Baris Göktepe (Berlin, DE); Cornelius Hellge (Berlin, DE); Thomas Schierl (Berlin, DE)

Assignee: Koninklijke Philips N.V.

H04W74/0841H04W72/0446H04W72/1263H04W74/0866

Abstract

Claims (94)

1. A device comprising:

an interface circuit, wherein the interface circuit is arranged to transmit a first signal;

a processor circuit and a memory circuit, wherein the memory is arranged to store instructions for the processor circuit,

wherein the processor circuit is arranged to provide the first signal so as to comprise a random access preamble,

wherein the processor circuit is arranged to select the random access preamble such that the random access preamble is associated with a transmission information,

wherein the processor circuit is arranged to transmit a second signal after transmitting the first signal,

wherein the second signal comprises second information related to the transmission information,

wherein the processor circuit is arranged to transmit a contention resolution signal between transmitting the first signal and transmitting the second signal.

2. The device of claim 1 , wherein the transmission information is based on one of the group consisting of identifier of the device, arrival of a message, pre-configuration of the network, device class, service class of the message, priority class of the message, reliability class of the message, latency class of the message, message type, message content, device priority, service policy or channel occupancy/quality measure.

3. The device of claim 1 ,

wherein the processor circuit is arranged to receive a Quality of Service information related to the transmission information,

wherein the circuit is arranged to select the random access preamble based on the Quality of Service information.

4. The device of claim 3 , wherein the processor circuit is arranged to use a predetermined resource for transmitting the second signal.

5. The device of claim 4 , wherein the predetermined resource is dedicated to the device or the processor circuit is arranged to select the predetermined resource from a pool of predetermined resources.

6. The device of claim 1 , wherein the transmission information is related to data obtained by the device.

7. The device of claim 1 ,

wherein the processor circuit is arranged to receive information,

wherein the information indicates a message,

wherein the message is transmitted with the interface circuit,

wherein the processor circuit selects the random access preamble so as to at least partially represent the message based on the information.

8. The device of claim 1 ,

wherein the processor circuit is arranged to select the random access preamble based on the transmission information a plurality of random access preambles,

wherein the plurality of random access preambles comprises at least one first random access preamble,

wherein the plurality of random access preambles is a portion of random access preambles.

9. The device of claim 8 ,

wherein the portion is one of a plurality of portions,

wherein each portion of the plurality of portions comprise at least one random access preamble,

wherein each portion of the plurality of portions is associated with a portion identifier,

wherein the portion identifier indicates a first information,

wherein the random access preamble of a portion is associated with a second information.

10. The device of claim 9 , wherein the plurality of portions comprise preambles that are orthogonal.

11. The device of claim 9 ,

wherein the first information is related to at least one of the group consisting of information indicating an identifier of the device, information indicating a device class of the device, and information indicating a service class of the transmission information,

wherein the second information is related to at least one of the group consisting of information indicating the transmission information, information indicating a service class of the transmission information, and information indicating a reliability measure of the device/observation.

12. The device of claim 1 ,

wherein the first signal is related to the transmission information,

wherein the random access preamble is a first random access preamble related to the transmission information,

wherein the processor circuit is arranged to transmit a second signal,

wherein the second signal is unrelated to the transmission information,

wherein the processor circuit is arranged to transmit a second random access preamble so as to reserve resources,

wherein the resource are for transmitting the second signal.

13. The device of claim 12 ,

wherein the processor circuit is arranged to select the first random access preamble from a first plurality of random access preambles,

wherein the processor circuit is arranged to select the second random access preamble from a second plurality of random access preambles.

14. The device of claim 1 , wherein the processor circuit is arranged to use a resource of a plurality of predetermined resources dedicated for transmitting the first signal to a transmission of transmission information-related signals.

15. The device of claim 1 ,

wherein the processor circuit is arranged to receive scheduling information,

wherein the scheduling information indicates a scheduled resource,

wherein the processor circuit is arranged to use the scheduled resource for transmitting the second signal.

16. The device of claim 1 ,

wherein the processor circuit is arranged to transmit the random access preamble as a first random access preamble so as to indicate a message class of the first signal,

wherein the processor circuit is arranged to transmit a second random access preamble,

wherein the second random access preamble is for contention resolution.

17. The device of claim 1 ,

wherein the processor circuit is arranged to a second signal subsequent to the first signal,

wherein the second signal is for contention resolution;

wherein a first transmission is one of the first signal and the second signal,

wherein a second transmission is one of the first signal and the second signal,

wherein the first transmission is different from the second transmission,

wherein the processor circuit is arranged to transmit the first transmission synchronized with a second device,

wherein the processor circuit is arranged to transmit the first wireless signal and the second wireless signal unsynchronized with the second device or with an individualized timing at the second device.

18. The device of claim 17 ,

wherein the processor circuit is arranged to transmit the first signal and the second signal with the individualized timing at the second device,

wherein the individualized timing for each of the first signal and the second signal is same.

19. The device of claim 17 , wherein the processor circuit is arranged to choose a time value for the timing based on the transmission information or a pre-configured information.

20. The device of claim 17 ,

wherein the processor circuit is arranged to transmit the first signal and the second signal with the individualized timing at the second device,

wherein the individualized timing for each of the first signal and the second signal is different.

21. A device comprising:

a processor circuit and a memory circuit, wherein the memory is arranged to store instructions for the processor circuit,

wherein the processor circuit is arranged to provide a random access resource,

wherein the random access resource is used by a third device for a random access procedure for transmitting a first signal,

wherein the first signal comprises a first random access preamble of a plurality of random access preambles,

wherein the processor circuit is arranged to associate the first random access preamble received with a first signal to a transmission information,

wherein the transmission information is reported by the third device,

wherein the processor circuit is arranged to not associate a second random access preamble received with a second signal with the transmission information.

22. The device of claim 21 ,

wherein the processor circuit is arranged to allow communication between the device and a first device and a second device,

wherein the processor circuit is arranged to associate a random access preamble,

wherein the random access preamble is transmitted by the first device with a first transmission information,

wherein the processor circuit is arranged to associate the random access preamble transmitted by the second device with a second transmission information,

wherein the first transmission information is different from the second transmission information.

23. The device of claim 21 , wherein the processor circuit is arranged to interpret the random access preamble at least as part of payload data transmitted by the device.

24. The device of claim 21 ,

wherein the processor circuit is arranged to receive the first signal,

wherein the processor circuit is arranged to identify the transmission information based on the random access preamble,

wherein the processor circuit is arranged to perform a contention resolution after having identified the transmission information.

25. The device of claim 24 ,

wherein the random access preamble is associated with an identifier,

wherein the processor circuit is arranged to perform the contention resolution based on a transmission of the identifier so as to initiate a random access procedure of devices having transmitted a first signal comprising the random access preamble associated with the identifier.

26. The device of claim 21 , wherein the processor circuit is arranged to broadcast information indicating an association of the transmission information with the random access preamble in a system information block of a communication scheme.

27. The device of claim 21 ,

wherein the processor circuit is arranged to evaluate the random access resource for a first random access preamble indicating a group of devices,

wherein the processor circuit is arranged to evaluate a second random access preamble indicating an identifier of the third device.

Assignments (4)

Priority Claims (1)

Continuity (2)

References Cited (28)