IP Library Granted Patent US 11,929,326
Granted Patent B2
US 11,929,326 · App. 17/556,134 · Granted Mar 12, 2024

Method of forming graphene barrier layer in interconnect structure

Inventors: Shin-Yi Yang (New Taipei, TW); Ming-Han Lee (Taipei, TW); Shau-Lin Shue (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L23/53238H01L21/324H01L21/76876H01L23/5226
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Quick Facts
Patent No.
US 11,929,326
App. No.
17/556,134
Granted
Mar 12, 2024
Kind
B2
Abstract

Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

Claims (46)

1. A method, comprising:

forming a first contact feature in a first dielectric layer over a workpiece;

forming a second dielectric layer over the first contact feature and the first dielectric layer;

forming a via opening in the second dielectric layer to expose a portion of the first contact feature;

depositing a seed metal layer in the via opening and over the second dielectric layer;

patterning the seed metal layer to expose a portion of the second dielectric layer;

depositing a third dielectric layer over the exposed portion of the second dielectric layer;

depositing a carbon layer over the seed metal layer and the third dielectric layer; and

annealing the workpiece to form a graphene layer between the seed metal layer and the third dielectric layer.

2. The method of claim 1 , wherein the depositing of the seed metal layer comprises depositing the seed metal layer using physical vapor deposition.

3. The method of claim 1 , further comprising:

after the depositing of the third dielectric layer, planarizing the workpiece to expose a top surface of the patterned seed metal layer.

4. The method of claim 1 , wherein the seed metal layer comprises a surface that is catalytic to graphene formation.

5. The method of claim 4 , wherein the seed metal layer comprises nickel, cobalt, iron, copper (Cu), or cupronickel.

6. The method of claim 4 , wherein the surface comprises a surface along a face-centered cubic (FCC) (111) plane, a surface along a hexagonal close-packed (HCP) (0001) plane, or a surface along an FCC (110) plane.

7. The method of claim 1 , wherein the annealing of the workpiece comprises annealing the workpiece at a temperature between 200° C. and 1200° C.

8. The method of claim 1 , further comprising:

after the annealing of the workpiece, removing the carbon layer.

9. The method of claim 1 , wherein the carbon layer is amorphous.

10. The method of claim 1 , wherein the annealing of the workpiece comprises a pressure between 2 atmosphere and 30 atmosphere.

11. The method of claim 1 , wherein, after the annealing, the graphene layer is also disposed between the seed metal layer and the second dielectric layer.

12. A method, comprising:

receiving a workpiece comprising a first contact feature in a first dielectric layer;

depositing an etch stop layer over the workpiece;

depositing a second dielectric layer over the etch stop layer;

forming a via opening through the second dielectric layer and the etch stop layer to expose a portion of the first contact feature;

depositing a seed metal layer in the via opening and over the second dielectric layer;

patterning the seed metal layer to expose a portion of the second dielectric layer;

depositing a third dielectric layer over the patterned seed metal layer and the exposed portion of the second dielectric layer;

depositing a carbon layer over the seed metal layer and the third dielectric layer; and

annealing the workpiece to form a graphene layer between the seed metal layer and the third dielectric layer, between the seed metal layer and the second dielectric layer, between the seed metal layer and the etch stop layer, and between the seed metal layer and the first contact feature.

13. The method of claim 12 , wherein the patterning is performed without use of any halogen-based reactant gases.

14. The method of claim 12 , wherein the depositing of the carbon layer comprises use of methane or ethene.

15. The method of claim 12 , wherein the depositing of the carbon layer comprises a temperature between room temperature and 400° C.

16. The method of claim 12 , wherein the carbon layer comprises a thickness between 5 Å and 100 Å.

17. A method, comprising:

receiving a workpiece that includes:

a first contact feature in a first dielectric layer,

a second dielectric layer over the first contact feature and the first dielectric layer,

a seed metal layer comprising a via portion and a line portion disposed over the via portion, wherein the via portion extends through the second dielectric layer to couple to the first contact feature and a portion of the line portion is disposed directly over a portion of the second dielectric layer, and

a third dielectric layer disposed over the line portion and the second dielectric layer;

depositing an amorphous carbon layer over the seed metal layer and the third dielectric layer; and

after the depositing of the amorphous carbon layer, annealing the workpiece to form a graphene layer between the seed metal layer and the third dielectric layer, between the seed metal layer and the second dielectric layer, and between the seed metal layer and the first contact feature.

18. The method of claim 17 , wherein the seed metal layer comprises a surface that is catalytic to graphene formation.

19. The method of claim 18 , wherein the seed metal layer comprises nickel, cobalt, iron, copper (Cu), or cupronickel.

20. The method of claim 18 , wherein the surface comprises a surface along a face-centered cubic (FCC) (111) plane, a surface along a hexagonal close-packed (HCP) (0001) plane, or a surface along an FCC (110) plane.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2021
From: YANG, SHIN-YI; LEE, MING-HAN; SHUE, SHAU-LIN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 058433/0076 →
Continuity (1)
Related Publication 20220115327A1 · Apr 14, 2022
Cited By (1)
US 12,557,632