Heterogeneous memory system

1. An apparatus comprising:

a first sensor layer, of a plurality of stacked sensor layers, including an array of pixels; and

one or more semiconductor layers of the plurality of stacked sensor layers located beneath the first sensor layer, the one or more semiconductor layers configured to process pixel data output by the array of pixels, the one or more semiconductor layers comprising:

a first memory to store most significant bits (“MSBs”) of data involved in the processing of the pixel data; and

a second memory to store least significant bits (“LSBs”) of the data,

wherein the first memory has a lower bit error rate (“BER”) than the second memory,

wherein the one or more semiconductor layers further comprise a machine learning (ML) model accelerator to process the pixel data, and wherein the data includes at least one of the pixel data, weights, and intermediate output data of the ML model, and

wherein the bit error rate of the first memory and the bit error rate of the second memory are based on a target classification error rate of processing of the pixel data by the ML model.

2. The apparatus of claim 1 , wherein the ML model includes a neural network.

3. The apparatus of claim 2 , wherein the neural network is a convolutional neural network.

4. The apparatus of claim 1 , wherein each of the first memory and the second memory includes a plurality of static random access memory (SRAM) cells.

5. The apparatus of claim 4 , wherein the SRAM cells of the first memory have larger transistor sizes than the SRAM cells of the second memory.

6. The apparatus of claim 5 , wherein each SRAM cell includes a pair of pull-up transistors and a pair of pull-down transistors to set a logical state stored in the SRAM cell, and a pair of access transistors to access the logical state stored in the SRAM cell; and

wherein in the SRAM cells of the first memory, a size of the pull-down transistor is larger than a size of the access transistor, and the size of the access transistor is larger than a size of the pull-up transistor.

7. The apparatus of claim 5 , wherein each SRAM cell includes a pair of pull-up transistors and a pair of pull-down transistors to set a logical state stored in the SRAM cell, and a pair of access transistors to access the logical state stored in the SRAM cell; and wherein in the SRAM cells of the second memory, a size of the pull-down transistor, a size of the access transistor, and a size of the access transistor are set to be equal.

8. The apparatus of claim 7 , wherein in the SRAM cells of the second memory, the size of the pull-down transistors, the size of the pull-up transistors, and the size of the access transistors are set to a minimum size defined by a process technology used to create such transistors.

9. The apparatus of claim 4 , wherein the SRAM cells of the first memory have a higher supply voltage than the SRAM cells of the second memory.

10. The apparatus of claim 4 , wherein the SRAM cells of the first memory are operated by read and write signals having a first signal level;

wherein the SRAM cells of the second memory are operated by read and write signals having a second signal level; and

wherein the first signal level is higher than the second signal level.

11. The apparatus of claim 4 , wherein the first memory further includes first sense amplifiers coupled with the SRAM cells of the first memory;

wherein the second memory further includes second sense amplifiers coupled with the SRAM cells of the second memory; and

wherein the first sense amplifiers operate with a larger current than the second sense amplifiers.

12. The apparatus of claim 11 , wherein the first sense amplifiers have larger transistor sizes than the second sense amplifiers.

13. The apparatus of claim 1 , wherein each of the first memory and the second memory includes a plurality of magnetoresistive random access memories (MRAM) devices, a plurality of resistive random access memories (RRAM), or memristors.

14. The apparatus of claim 13 , wherein the MRAM devices of the first memory are operated with a first write current to perform write operations;

wherein the MRAM devices of the second memory are operated with a second write current to perform write operations; and

wherein the first write current is larger than the second write current.

15. The apparatus of claim 13 , wherein the MRAM devices of the first memory are operated with a first write pulse to perform write operations;

wherein the MRAM devices of the second memory are operated with a second write pulse to perform write operations; and

wherein a duration of the first write pulse is longer than the second write pulse.

16. The apparatus of claim 13 , wherein the MRAM devices of the first memory are operated with a first read current to perform read operations;

wherein the MRAM devices of the second memory are operated with a second read current to perform read operations; and

wherein the first read current is larger than the second read current.

17. The apparatus of claim 13 , wherein the MRAM devices of the first memory are operated with a first read pulse to perform read operations;

wherein the MRAM devices of the second memory are operated with a second read pulse to perform read operations; and

wherein a duration of the first read pulse is longer than the second read pulse.

18. A head-mounted display (“HMD”) device comprising:

an image sensor; and

an electronic display, the electronic display configured to display images based on data received from a console device; and

wherein the image sensor is configured to transmit captured images to the console device, and wherein the image sensor comprises:

a first sensor layer, of a plurality of stacked sensor layers, including an array of pixels; and

one or more semiconductor layers of the plurality of stacked sensor layers located beneath the first sensor layer, the one or more semiconductor layers configured to process pixel data output by the array of pixels, the one or more semiconductor layers comprising a first memory to store most significant bits (“MSBs”) of data involved in the processing of the pixel data; and a second memory to store least significant bits (“LSBs”) of the data,

wherein the first memory has a lower bit error rate (“BER”) than the second memory,

wherein the one or more semiconductor layers further comprise a machine learning (ML) model accelerator configured to process the pixel data, and wherein the data includes at least one of the pixel data, weights, and intermediate output data of the ML model, and

wherein the bit error rate of the first memory and the bit error rate of the second memory are based on a target classification error rate of processing of the pixel data by the ML model.

19. The HMD apparatus of claim 18 , wherein the ML model includes a neural network.

20. The HMD apparatus of claim 19 , wherein the neural network is a convolutional neural network.