Automatic protection against runt pulses

1. An apparatus, comprising:

an adjustment circuit to:

receive a pulsed-width modulation (PWM) input;

generate an adjusted PWM signal based upon the PWM input;

determine that a first pulse of the PWM input is shorter than a runt signal limit;

in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit;

based upon extension of the first pulse, shorten a second pulse of the PWM input as included in the adjusted PWM signal, the second pulse immediately following the first pulse; and

output the adjusted PWM signal to an electronic device.

2. The apparatus of claim 1 , comprising a counter, the counter to begin a determination of a length of the first pulse of the PWM input after a prescribed delay between the PWM input and the output of the adjusted PWM signal.

3. The apparatus of claim 1 , wherein:

the PWM input includes a PWML signal and a PWMH signal;

the adjusted PWM signal includes an adjusted PWML signal and an adjusted PWMH signal;

the PWMH signal and the PWML signal to include PWM signals and to be complements of each other during a plurality of clock cycles;

the adjusted PWMH signal and the adjusted PWML signal to include PWM signals and to be complements of each other during a plurality of clock cycles; and

the adjustment circuit is to selectively adjust the PWMH signal to generate the adjusted PWMH signal and to selectively adjust the PWML signal to generate the adjusted PWML signal.

4. The apparatus of claim 3 , comprising a counter, the counter to continuously determine lengths of respective pulses of the PWMH signal, the counter to begin determination of a length of a respective pulse of the PWMH signal after a changed edge on the PWMH signal and after a changed edge on the adjusted PWMH signal since a last reset of the counter.

5. The apparatus of claim 3 , wherein:

the first pulse and a second pulse are of the PWMH signal;

the adjustment circuit is to, based upon extension of the first pulse, shorten the second pulse to generate the adjusted PWMH signal, the second pulse immediately following the first pulse;

the PWML signal includes a third pulse and a fourth pulse, the third pulse a complement of the first pulse, the fourth pulse a complement of the second pulse;

the adjustment circuit is to:

determine that the third pulse is a runt pulse;

extend the third pulse based upon the determination that third pulse is a runt pulse and, based upon extension of third pulse, shorten the fourth pulse to generate the adjusted PWML signal.

6. An apparatus, comprising:

an adjustment circuit to:

receive a pulsed-width modulation (PWM) input;

generate an adjusted PWM signal based upon the PWM input;

determine that a first pulse of the PWM input is shorter than a runt signal limit;

in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit; and

output the adjusted PWM signal to an electronic device;

wherein:

the PWM input includes a PWML signal and a PWMH signal;

the adjusted PWM signal includes an adjusted PWML signal and an adjusted PWMH signal;

the PWMH signal and the PWML signal to include PWM signals and to be complements of each other during a plurality of clock cycles;

the adjusted PWMH signal and the adjusted PWML signal to include PWM signals and to be complements of each other during a plurality of clock cycles; and

the adjustment circuit is to:

selectively adjust the PWMH signal to generate the adjusted PWMH signal and to selectively adjust the PWML signal to generate the adjusted PWML signal;

determine that the PWMH signal and the PWML signal are simultaneously at a logic low value for a duration of clock cycles at a time after the first pulse; and

preserve a state of the PWMH signal and the PWML signal at the logic low value for the duration of clock cycles in the adjusted PWMH signal and the adjusted PWML signal after the first pulse.

7. The apparatus of claim 6 , comprising:

a PWMH counter to count clock cycles beginning upon a changed edge of the PWMH signal and to determine whether a pulse of the PWMH signal is shorter than a runt count and thus classified as a runt pulse; and

a PWML counter to count clock cycles beginning upon a changed edge of the PWML signal and to determine whether a pulse of the PWML signal is shorter than the runt count and thus classified as a runt pulse;

wherein the adjustment circuit is to:

upon a determination that the PWML signal and the PWMH signal are simultaneously at the logic low value for the duration of clock cycles, add a value of the PWMH counter to the PWML counter to preserve the state of the PWMH signal and the PWMH signal at the logic low value for the duration of clock cycles in the adjusted PWMH signal and the adjusted PWML signal.

8. A method, comprising:

receiving a pulsed-width modulation (PWM) input;

generating an adjusted PWM signal based upon the PWM input;

determining that a first pulse of the PWM input is shorter than a runt signal limit;

wherein generating the adjusted PWM signal comprises:

extending the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit; and

based upon extension of the first pulse, shortening a second pulse of the PWM input as included in the adjusted PWM signal, the second pulse immediately following the first pulse; and

outputting the adjusted PWM signal to an electronic device.

9. The method of claim 8 , comprising beginning a determination of a length of the first pulse of the PWM input after a prescribed delay between the PWM input and the output of the adjusted PWM signal.

10. The method of claim 8 , wherein:

the PWM input includes a PWML signal and a PWMH signal;

the adjusted PWM signal includes an adjusted PWML signal and an adjusted PWMH signal;

the PWMH signal and the PWML signal include PWM signals and to be complements of each other during a plurality of clock cycles;

the adjusted PWMH signal and the adjusted PWML signal include PWM signals and to be complements of each other during a plurality of clock cycles; and

wherein generating the adjusted PWM signal comprises:

selectively adjusting the PWMH signal to generate the adjusted PWMH signal; and

selectively adjusting the PWML signal to generate the adjusted PWML signal.

11. The method of claim 10 , further comprising, with a counter, continuously determining lengths of respective pulses of the PWMH signal, including beginning determination of a length of a respective pulse of the PWMH signal after a changed edge on the PWMH signal and after a changed edge on the adjusted PWMH signal since a last reset of the counter.

12. The method of claim 10 , wherein:

the first pulse and a second pulse are of the PWMH signal;

wherein generating the adjusted PWM signal comprises, based upon extension of the first pulse, shortening the second pulse to generate the adjusted PWMH signal, the second pulse immediately following the first pulse;

the PWML signal includes a third pulse and a fourth pulse, the third pulse a complement of the first pulse, the fourth pulse a complement of the second pulse; and

wherein generating the adjusted PWM signal comprises:

determining that the third pulse is a runt pulse; and

extending the third pulse based upon the determination that third pulse is a runt pulse and, based upon extension of third pulse, shorten the fourth pulse to generate the adjusted PWML signal.

13. A method, comprising:

receiving a pulsed-width modulation (PWM) input;

generating an adjusted PWM signal based upon the PWM input;

determining that a first pulse of the PWM input is shorter than a runt signal limit;

wherein generating the adjusted PWM signal includes extending the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit; and

outputting the adjusted PWM signal to an electronic device;

wherein:

the PWM input includes a PWML signal and a PWMH signal;

the adjusted PWM signal includes an adjusted PWML signal and an adjusted PWMH signal;

the PWMH signal and the PWML signal include PWM signals and are complements of each other during a plurality of clock cycles;

the adjusted PWMH signal and the adjusted PWML signal include PWM signals and to be complements of each other during a plurality of clock cycles; and

wherein generating the adjusted PWM signal includes:

selectively adjusting the PWMH signal to generate the adjusted PWMH signal and selectively adjusting the PWML signal to generate the adjusted PWML signal;

determining that the PWMH signal and the PWML signal are simultaneously at a logic low value for a duration of clock cycles at a time after the first pulse; and

preserving a state of the PWMH signal and the PWML signal at the logic low value for the duration of clock cycles in the adjusted PWMH signal and the adjusted PWML signal after the first pulse.

14. The method of claim 13 , further comprising:

with a PWMH counter, counting clock cycles beginning upon a changed edge of the PWMH signal and determining whether a pulse of the PWMH signal is shorter than a runt count and thus classified as a runt pulse;

with a PWML counter, counting clock cycles beginning upon a changed edge of the PWML signal and determining whether a pulse of the PWML signal is shorter than the runt count and thus classified as a runt pulse; and

upon a determination that the PWML signal and the PWMH signal are simultaneously at the logic low value for the duration of clock cycles, adding a value of the PWMH counter to the PWML counter to preserve the state of the PWMH signal and the PWMH signal at the logic low value for the duration of clock cycles in the adjusted PWMH signal and the adjusted PWML signal.

15. A microcontroller, comprising:

a pulsed-width modulation (PWM) generation circuit to generate a PWM input; and

an adjustment circuit to:

receive the PWM input;

generate an adjusted PWM signal based upon the PWM input;

determine that a first pulse of the PWM input is shorter than a runt signal limit;

in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit;

based upon extension of the first pulse, shorten a second pulse of the PWM input as included in the adjusted PWM signal, the second pulse immediately following the first pulse; and

output the adjusted PWM signal to an electronic device.

16. The microcontroller of claim 15 , wherein the adjustment circuit comprises a counter, the counter to begin a determination of a length of the first pulse of the PWM input after a prescribed delay between the PWM input and the output of the adjusted PWM signal.

17. The microcontroller of claim 15 , wherein:

the PWM input includes a PWML signal and a PWMH signal;

the adjusted PWM signal includes an adjusted PWML signal and an adjusted PWMH signal;

the PWMH signal and the PWML signal are to include PWM signals and to be complements of each other during a plurality of clock cycles;

the adjusted PWMH signal and the adjusted PWML signal to include PWM signals and to be complements of each other during a plurality of clock cycles; and

the adjustment circuit is to selectively adjust the PWMH signal to generate the adjusted PWMH signal and to selectively adjust the PWML signal to generate the adjusted PWML signal.

18. A microcontroller, comprising:

a pulsed-width modulation (PWM) generation circuit to generate a PWM input, the PWM input includes a PWML signal and a PWMH signal, which PWML signal and PWMH signal are complements of each other during a plurality of clock cycles; and

an adjustment circuit to:

receive the PWM input;

generate an adjusted PWM signal based upon the PWM input;

determine that a first pulse of the PWM input is shorter than a runt signal limit;

in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit; and

output the adjusted PWM signal to an electronic device;

wherein:

the adjusted PWM signal is to include an adjusted PWML signal and an adjusted PWMH signal which adjusted PWMH signal and the adjusted PWML signal are to be complements of each other during a plurality of clock cycles; and

the adjustment circuit is to:

selectively adjust the PWMH signal to generate the adjusted PWMH signal and to selectively adjust the PWML signal to generate the adjusted PWML signal;

determine that the PWMH signal and the PWML signal are simultaneously at a logic low value for a duration of clock cycles at a time after the first pulse; and

preserve a state of the PWMH signal and the PWML signal at the logic low value for the duration of clock cycles in the adjusted PWMH signal and the adjusted PWML signal after the first pulse.