Multi-level structures and methods for switched-mode power supplies
Methods for modifying converter cells for switched-mode power converters, and corresponding power converter cells. The modified converter cells exhibit reduced inductance requirements, enable use of lower voltage and smaller switches, provide improved power density and efficiency, and provide for improved input/output voltage dynamic range. Embodiments of the methods generate converter cell topologies having 3 or more node voltage levels by successively applying a “split switches and connect through a capacitor” operation. The inventive processes, or variants of those processes, may be applied to converter cell topologies that are 2-level converter cells including at least one inductance and two switches, and particularly 2-level converter cells including either (1) an order of at least 3 (i.e., 3 or more energy storage elements in some combination of inductances and capacitances, but with at least one inductance) and at least 2 switches, or (2) at least 1 designed-in inductance and at least 4 switches.
1. At least two converter cells, each converter cell including at least 3 node voltage levels and made by modifying a 2-level converter cell that includes either (1) at least 3 designed-in energy storage elements, the at least 3 designed-in energy storage elements including at least one designed-in inductance, and at least 2 initial switches, or (2) at least 1 designed-in inductance and at least 4 initial switches,
wherein each converter cell includes a first pair of replacement switches replacing a first initial switch within the 2-level converter cell and a second pair of replacement switches replacing a second initial switch within the 2-level converter cell,
wherein the first and second initial switches are not conductive at the same time during steady-state operation,
wherein a first intermediate node between the first pair of replacement switches and a second intermediate node between the second pair of replacement switches are configured to be coupled to a capacitor,
wherein each converter cell is coupled to a common input terminal and provides an output through one output designed-in inductance of the at least one designed-in inductances, and
wherein the output of each converter cell is coupled to a common output terminal and the output designed-in inductances of at least two of the at least two converter cells are magnetically coupled with opposite poles.
2. The at least two converter cells of claim 1 , wherein one of the first or second initial switches is a diode functioning as a switch.
3. The at least two converter cells of claim 1 , wherein each of the 2-level converter cells is a 2-level non-isolated Ćuk converter cell.
4. The at least two converter cells of claim 1 , wherein each of the 2-level converter cells is a 2-level isolated Ćuk converter cell.
5. The at least two converter cells of claim 1 , wherein each of the 2-level converter cells is one of a 2-level single-ended primary-inductor converter (SEPIC) converter cell or a 2-level Zeta converter cell.
6. The at least two converter cells of claim 1 , wherein each of the 2-level converter cells is a 2-level Flyback converter cell.
7. The at least two converter cells of claim 1 , wherein each of the 2-level converter cells is a 2-level Forward converter cell.
8. A method for constructing at least two converter cells, each converter cell having at least 3 node voltage levels, by modifying a 2-level converter cell including either (1) at least 3 designed-in energy storage elements, the at least 3 designed-in energy storage elements including at least one designed-in inductance, and at least 2 initial switches, or (2) at least 1 designed-in inductance and at least 3 initial switches, the method including:
(a) selecting a first initial switch and a second initial switch within each of the 2-level converter cells that are not conductive at the same time during steady-state operation;
(b) splitting the selected first initial switch into a first 2 series-connected replacement switches, thereby forming a first intermediate node between the first 2 series-connected replacement switches; and
(c) splitting the selected second initial switch into a second 2 series-connected replacement switches, thereby forming a second intermediate node between the second 2 series-connected replacement switches; and
(d) coupling the formed first intermediate node and the formed second intermediate node through a capacitor;
wherein each converter cell is coupled to a common input terminal and provides an output through one output designed-in inductance of the at least one designed-in inductances, and
wherein the output of each converter cell is coupled to a common output terminal and the output designed-in inductances of at least two of the at least two converter cells are magnetically coupled with opposite poles.
9. The method of claim 8 , wherein at least one of the first or second initial switches comprises a diode functioning as a switch.
10. The method of claim 8 , wherein splitting the first or second selected initial switch into the respective first or second 2 series-connected switches comprises retaining the first or second selected initial switch and coupling the retained first or second initial switch in series with an added switch to form the respective first or second 2 series-connected replacement switches.
11. The method of claim 8 , wherein the at least one designed-in inductance of the at least 3 designed-in energy storage elements includes 2 or more designed-in inductances.
12. The method of claim 8 , wherein the at least 3 initial switches include 4 or more initial switches.
13. The method of claim 12 , wherein each of the 2-level converter cells is a 2-level non-isolated Ćuk converter cell.
14. The method of claim 12 , wherein each of the 2-level converter cells is a 2-level isolated Ćuk converter cell.
15. The method of claim 12 , wherein each of the 2-level converter cells is one of a 2-level single-ended primary-inductor converter (SEPIC) converter cell or a 2-level Zeta converter cell.
16. The method of claim 12 , wherein each of the 2-level converter cells is a 2-level Flyback converter cell.
17. The method of claim 12 , wherein each of the 2-level converter cells is a 2-level Forward converter cell.