Storage system with multiplane segments and cooperative flash management
This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.
1. A storage apparatus comprising:
at least one host processor; and
one or more storage drives, a given one of the one or more storage drives comprising flash memory having planes, each of the planes having erase units, each of the erase units being associated with exactly one of the planes, the flash memory being organized so as to have subdivisions corresponding to respective, mutually-exclusive sets of the erase units, each of the mutually-exclusive sets comprising erase units that are in respective ones of the planes;
wherein the given one of the one or more storage drives further comprises circuitry to
transmit to the at least one host processor information representing one or more of the subdivisions of the given one of the one or more storage drives, to identify associated subdivision size and associated subdivision logical address,
store metadata respective to the subdivisions of the given one of the one or more storage drives, identify a need for maintenance for one of the subdivisions of the given one of the one or more storage drives dependent on the respective metadata, and a logical address associated with the need for maintenance in the one of the subdivisions, and transmit to the at least one host processor the logical address associated with the need for maintenance; and
wherein the at least one host processor is to transmit maintenance command to the given one of the one or more storage drives, the maintenance command being addressed to the one of the subdivisions for which the need for maintenance was identified, to cause the given one of the one or more storage drives to responsively erase two or more of the erase units corresponding to the one of the subdivisions for which the need for maintenance was identified, including erase units in at least two different ones of the planes.
2. The storage apparatus of claim 1 wherein the circuitry comprises at least one drive processor and instructions stored on at least one non-transitory storage medium, said instructions, when executed, to cause the at least one drive processor to control:
the transmission to the at least one host processor of the information representing the at least one of the subdivisions;
the storage of the metadata respective to the subdivisions;
the identification of the need for maintenance, and of the logical address associated with the need for maintenance;
the transmission to the at least one host processor of the logical address associated with the need for maintenance; and
receipt of the maintenance command from the at least one host processor, and the responsive erasure of the two or more of the erase units corresponding to the one of the subdivisions for which the need for maintenance was identified.
3. The storage apparatus of claim 1 wherein the given one of the one or more storage drives comprises nonvolatile memory and wherein the given one of the one or more storage drives is to store the metadata in the nonvolatile memory.
4. The storage apparatus of claim 1 wherein the circuitry is to perform the identification of the logical address associated with the need for maintenance on an unsolicited basis.
5. The storage apparatus of claim 1 wherein the circuitry is to compare the metadata with at least one threshold and is to identify the need for maintenance dependent on the comparison.
6. The storage apparatus of claim 1 wherein the circuitry is to store the metadata, for at least one of the subdivisions, on a basis that is respective to each erase unit in the mutually-exclusive set which is respective to the at least one of the subdivisions.
7. The storage apparatus of claim 6 wherein the given one of the one or more storage drives comprises circuitry to receive a query from the at least one host processor and to responsively transmit to the at least one host processor information dependent on wear of a specific erase unit corresponding to one of the subdivisions of the given one of the one or more storage drives.
8. The storage apparatus of claim 1 wherein:
the metadata is dependent on an erase count of associated physical memory space; and
the circuitry is to compare the metadata with at least one threshold and is to identify the need for maintenance dependent on the comparison.
9. The storage apparatus of claim 1 wherein:
the metadata is dependent on a time since associated physical memory space was programmed; and
the circuitry is to compare the metadata with at least one threshold and is to identify the need for maintenance dependent on the comparison.
10. The storage apparatus of claim 1 wherein the given one of the one or more storage drives comprises circuitry to receive a query from the at least one host processor and to responsively transmit to the at least one host processor query response information dependent on wear, the wear being determined from the metadata.
11. The storage apparatus of claim 1 wherein the given one of the one or more storage drives comprises circuitry to receive a query from the at least one host processor and to responsively transmit to the at least one host processor query response information dependent on a time since data was programmed, the time since data was programmed being determined from the metadata.
12. The storage apparatus of claim 1 wherein:
the metadata is dependent on a time since associated physical memory space was programmed; and
the circuitry is to unsolicitedly compare the metadata to at least one threshold and is to identify the need for maintenance dependent on the comparison.
13. The storage apparatus of claim 1 wherein:
the metadata is dependent on an erase count of physical memory space, and
the circuitry is to update the metadata in a manner responsive to erasure of associated physical memory space, performed as a function of maintenance commands received by the given one of the one or more storage drives.
14. The storage apparatus of claim 1 wherein the given one of the one or more storage drives further comprises circuitry to detect a failure condition of one of the erase units, and to transmit information to the at least one host processor that identifies a subdivision corresponding to the one of the erase units for which the failure condition was detected.
15. The storage apparatus of claim 1 wherein:
the given one of the one or more storage drives further comprises circuitry to detect a failure condition of one of the erase units of the flash memory; and
the given one of the one or more storage drives is further to, for an incoming write request addressed to a subdivision corresponding to an erase unit for which the failure condition has been detected, transmit to the at least one host processor a notification of a write failure and logical address information identifying the subdivision which corresponds to the one of the erase units for which the failure condition has been detected.
16. The storage apparatus of claim 1 wherein the given one of the one or more storage drives is to, for each one of a set of incoming read requests having sequential addressing:
identify a commonly addressed page; and
concurrently retrieve read data corresponding to the commonly address page from respective ones of the planes.
17. The storage apparatus of claim 1 wherein:
the given one of the one or more storage drives comprises circuitry to receive write requests from the at least one host processor, and to service the write requests by transferring associated data between the at least one host processor and the flash memory; and
for each one of the write requests, the given one of the storage drives is to generate an address offset that designates a storage location within an addressed one of the subdivisions and is to transmit the address offset to the at least one host processor.
18. The storage apparatus of claim 1 wherein:
the given one of the one or more storage drives further comprises circuitry to receive read requests and write requests from the at least one host processor and to service the read requests and the write requests by transferring associated data between the at least one host processor and the flash memory; and
the given one of the one or more storage drives further comprises circuitry to identify a physical write destination for write data accompanying one of the write requests, to identify an address value corresponding to the identified physical write destination, and to transmit the identified address value to the at least one host processor;
each read request received by the given one of the one or more storage drives is to be accompanied by a logical read address, each logical read address having a first nonexhaustive address portion which selects one of the subdivisions according to a value of the first nonexhaustive portion, each logical read address having a second nonexhaustive address portion which is to select a storage location associated with the selected one of the subdivisions; and
the logical read address for each read request which seeks retrieval of the write data is dependent on the identified address value which was transmitted to the at least one host processor.
19. The storage apparatus of claim 1 wherein for at least one write request addressed to the given one of the storage drives, an addressed one of the subdivisions corresponds to an integer number of erase units for which a failure condition has not been detected, and wherein the given one of the storage drives further comprises circuitry to, for a write address accompanying the write request, generate an address offset which corresponds to a location within a sequential range of locations that corresponds to the integer number of erase units.
20. The storage apparatus of claim 1 wherein:
the given one of the one or more storage drives further comprises circuitry to receive read requests and write requests from the at least one host processor, and to service the read requests and the write requests by transferring associated data between the at least one host processor and the flash memory; and
each read request is accompanied by a logical read address, each logical read address having a first nonexhaustive address portion which is to select one of the subdivisions according to a value of the first nonexhaustive portion, each logical read address having a second nonexhaustive address portion which is translated to a physical memory location differently depending on the one of the subdivisions selected from the associated first address portion.
21. The storage apparatus of claim 1 wherein the circuitry is also to store, for one or more respective ones of the subdivisions, information dependent on at least one of a number of times that at least one erase unit of the respective one of the subdivisions has been erased or existence of read error detected for the respective one of the subdivisions.
22. The storage apparatus of claim 1 wherein:
the circuitry is further to store information identifying a number of flash memory structures and is to transmit to the at least one host processor the information identifying the number of flash memory structures;
the given one of the one or more storage drives further comprises circuitry to receive from the at least one host processor data access requests which are dependent, for an addressed one of the subdivisions of the associated storage drive, on the information transmitted to the at least one host processor drive identifying the number of flash memory structures.
23. The storage apparatus of claim 22 wherein the circuitry to receive the data access requests is to fulfill the data access requests by issuing commands to the flash memory for which a quantum of flash memory selected by the commands is dependent on the information transmitted to the at least one host processor identifying the number of flash memory structures.
24. The storage apparatus of claim 1 wherein, the circuitry is to:
track additional metadata for each of the subdivisions, where the additional metadata indicates an extent to which an associated portion of the flash memory can continue to receive additional write data without being erased; and
transmit information to the at least one host processor dependent on said additional metadata.
25. The storage apparatus of claim 1 wherein the given one of the one or more storage drives comprises circuitry to:
track additional metadata, which indicates an extent to which memory comprising at least one physical erase unit corresponding to a given one of the subdivisions can continue to receive additional write data without being erased; and
for a given incoming write request which designates the given one of the subdivisions, update the corresponding additional metadata.
26. The storage apparatus of claim 1 wherein the given one of the one or more of storage drives is to receive write requests, with associated addressing and associated data, and wherein the circuitry is to, for write requests for which the associated addressing specifies a sequence of addresses, write the associated data to erase units in respective ones of the planes using a common address offset.
27. The storage apparatus of claim 1 wherein:
the given one of the one or more storage drives is a first drive and the maintenance command is a first maintenance command;
the one or more storage drives also comprises a second drive, the second drive also comprising flash memory having planes, each of the planes of the second drive also having erase units, each of the erase units of the second drive being associated with exactly one of the planes of the second drive, the flash memory of the second drive being organized so as to have subdivisions corresponding to respective, mutually-exclusive sets of the erase units of the second drive, each of the mutually-exclusive sets corresponding to subdivisions of the flash memory of the second drive comprising erase units that are in respective ones of the planes of the second drive;
wherein the second drive further comprises circuitry to
transmit to the at least one host processor information representing one or more of the subdivisions of the second drive, to identify associated subdivision size and associated subdivision logical address,
store metadata respective to the subdivisions of the second drive, identify a need for maintenance for one of the subdivisions of the second drive dependent on the respective metadata stored by the second drive, and a logical address associated with the one of the subdivisions of the second drive for which the need for maintenance was identified by the second drive, and transmit to the at least one host processor the logical address associated with the need for maintenance in the second drive; and
wherein the at least one host processor is to transmit a second maintenance command, to the second drive, the second maintenance command being addressed to the one of the subdivisions of the second drive for which the need for maintenance was identified by the circuitry of the second drive, the second maintenance command to cause the second drive to responsively erase two or more of the erase units of the second drive each corresponding to the one of the subdivisions of the second drive for which the need for maintenance was identified by the second drive, including erase units in at least two different ones of the planes of the second drive.