Granted Patent B2

US 12,237,953 · App. 17/564,867 · Granted Feb 25, 2025

Inventors: Timothy M. Hollis (Meridian, ID); Markus Balb (Ottobrunn, DE); Ralf Ebert (Munich, DE)

Assignee: Micron Technology, Inc.

H04L25/4917G11C7/1048G11C7/1057G11C7/1084G11C7/1096H04L25/4921

Abstract

Claims (56)

1. An apparatus, comprising:

an array of memory cells;

a controller configured to control operation of memory cells in the array of memory cells;

a signaling interface coupled with the array of memory cells and configured to generate a signal modulated using a first modulation scheme based at least in part on a logic state read from the array of memory cells; and

a receiver configured to determine the logic state represented by the signal modulated using the first modulation scheme communicated across at least one channel of a plurality of channels between the array of memory cells and the controller.

2. The apparatus of claim 1 , further comprising:

an interposer operatively coupled with the array of memory cells and the controller, wherein the interposer comprises the plurality of channels between the array of memory cells and the controller.

3. The apparatus of claim 1 , further comprising:

a substrate coupled with the controller via a second plurality of channels.

4. The apparatus of claim 1 , wherein the signaling interface comprises:

a driver coupled with the controller and configured to generate the signal.

5. The apparatus of claim 4 , wherein the driver comprises:

a pull-up circuit configured to increase an amplitude of the signal; and

a pull-down circuit configured to decrease the amplitude of the signal.

6. The apparatus of claim 1 , wherein:

the signal communicated across the at least one channel comprises a multi-level signal; and

the at least one channel comprises a unidirectional channel.

7. The apparatus of claim 1 , wherein the receiver comprises:

one or more comparators, each comparator configured to compare the signal to a respective reference voltage of one or more reference voltages.

8. The apparatus of claim 7 , wherein the receiver further comprises:

a decoder configured to determine the logic state represented by the signal based at least in part on a respective output of each comparator of the one or more comparators.

9. The apparatus of claim 1 , wherein the first modulation scheme comprises a non-return-to-zero (NRZ) scheme, a unipolar encoding scheme, a bipolar encoding scheme, a Manchester encoding scheme, a two-level pulse amplitude modulation (PAM) scheme, a four-level PAM scheme, an eight-level PAM scheme, a quadrature amplitude modulation (QAM) scheme, quadrature phase shift keying, or a combination thereof.

10. A method, comprising:

identifying, by a controller of a memory device, information to be written to an array of memory cells;

generating, by the controller, a signal that represents a plurality of bits of the identified information, wherein the signal is modulated using a first modulation scheme based at least in part on a logic state read from the array of memory cells; and

transmitting, by the controller, the signal to the array of memory cells across at least one channel of a plurality of channels located between the controller and the array of memory cells.

11. The method of claim 10 , further comprising:

receiving, by a transmission circuit, data from the array of memory cells based at least in part on transmitting the signal; and

determining, by the controller, an instruction comprising an adjustment to an amplitude of the signal.

12. The method of claim 11 , further comprising:

biasing, by a pull-up circuit, the signal to increase the amplitude of the signal based at least in part on the instruction.

13. The method of claim 11 , further comprising:

biasing, by a pull-down circuit, the signal to decrease the amplitude of the signal based at least in part on the instruction.

14. The method of claim 10 , further comprising:

comparing, by the array of memory cells, the signal to one or more voltage thresholds;

identifying, by the array of memory cells, the plurality of bits represented by the signal based at least in part on comparing the signal to the one or more voltage thresholds; and

writing, by the array of memory cells, the plurality of bits represented by the signal to one or more memory cells of the array of memory cells.

15. An apparatus, comprising:

an array of memory cells; and

a controller coupled with the array of memory cells and configured to cause the apparatus to:

identify information to be written to an array of memory cells;

generate a signal that represents a plurality of bits of the identified information, wherein the signal is modulated using a first modulation scheme based at least in part on a logic state read from the array of memory cells; and

transmit the signal to the array of memory cells across at least one channel of a plurality of channels located between the controller and the array of memory cells.

16. The apparatus of claim 15 , wherein the controller is further configured to cause the apparatus to:

receive data from the array of memory cells based at least in part on transmitting the signal; and

determine an instruction comprising an adjustment to an amplitude of an output signal that is based at least in part on the received data.

17. The apparatus of claim 16 , wherein the controller is further configured to cause the apparatus to:

bias the output signal to increase or decrease the amplitude of the output signal based at least in part on the instruction.

18. The apparatus of claim 15 , wherein the controller is further configured to cause the apparatus to:

compare the signal to one or more voltage thresholds;

identify the plurality of bits represented by the signal based at least in part on comparing the signal to the one or more voltage thresholds; and

write the plurality of bits represented by the signal to one or more memory cells of the array of memory cells.

19. The apparatus of claim 15 , wherein:

the signal communicated across the at least one channel comprises a multi-level signal; and

the at least one channel comprises a unidirectional channel.

20. The apparatus of claim 15 , wherein the first modulation scheme comprises a non-return-to-zero (NRZ) scheme, a unipolar encoding scheme, a bipolar encoding scheme, a Manchester encoding scheme, a two-level pulse amplitude modulation (PAM) scheme, a four-level PAM scheme, an eight-level PAM scheme, a quadrature amplitude modulation (QAM) scheme, quadrature phase shift keying, or a combination thereof.

Continuity (5)

References Cited (221)