IP Library Granted Patent US 12,066,955
Granted Patent B2
US 12,066,955 · App. 17/565,779 · Granted Aug 20, 2024

System and method for enhancing throughput during data transfer

Inventors: Aneeshwar Danda (Germantown, MD); Robert H. Lager (Germantown, MD); Sahithi Vemuri (Germantown, MD)
Assignee: HUGHES NETWORK SYSTEMS, LLC
G06F13/1668
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Quick Facts
Patent No.
US 12,066,955
App. No.
17/565,779
Granted
Aug 20, 2024
Kind
B2
Abstract

Systems and method for transferring data are disclosed herein. In an embodiment, a method of transferring data includes reading a plurality of bytes from a first memory, discarding first bytes of the plurality of bytes, realigning second bytes of the plurality of bytes, and storing the realigned second bytes in a second memory.

Claims (53)

1. A method of transferring data between a first memory and a second memory, the method comprising

reading a plurality of bytes from the first memory,

discarding first bytes of the plurality of bytes;

realigning second bytes of the plurality of bytes in a burst buffer based on a destination offset of the second memory; and

transferring the realigned second bytes from the burst buffer to the second memory.

2. The method of claim 1 , which includes determining a source offset for the first memory.

3. The method of claim 2 , which includes separating the plurality of bytes into a plurality of beats based on the source offset.

4. The method of claim 2 , which includes reading the plurality of bytes from the first memory based on the source offset.

5. The method of claim 1 , which includes

determining the destination offset for the second memory prior to reading the plurality of bytes from the first memory.

6. The method of claim 1 , wherein

the first memory is offset by N,

the second memory is offset by M, and

realigning the second bytes of the plurality of bytes in the burst buffer includes placing a byte read at position N of the first memory to position M of the burst buffer.

7. A system including a controller programmed to perform the method of claim 1 .

8. A method of transferring data between a first memory and a second memory, the method comprising:

generating a read command associated with the first memory;

reading a plurality of bytes from the first memory;

storing the read command in one or more first frames of a burst buffer;

realigning the plurality of bytes in one or more second frames of the burst buffer based on a destination offset of the second memory; and

transmitting the burst buffer to the second memory.

9. The method of claim 8 , which includes determining a source offset for the first memory.

10. The method of claim 9 , which includes separating the plurality of bytes into a plurality of beats based on the source offset.

11. The method of claim 9 , which includes reading the plurality of bytes from the first memory based on the source offset.

12. The method of claim 8 , which includes determining the destination offset for the second memory prior to generating the read command.

13. A system including a controller programmed to perform the method of claim 8 .

14. A method of transferring data between a first memory and a second memory having different architectures, the method comprising:

determining a source offset for the first memory;

determining a destination offset for the second memory;

reading a plurality of bytes from the first memory based on the source offset;

realigning the plurality of bytes in a burst buffer based on the destination offset; and

transferring the realigned plurality of bytes to the second memory.

15. The method of claim 14 , wherein

the destination offset is different from the source offset.

16. The method of claim 14 , which includes discarding first bytes of the plurality of bytes,

wherein realigning the plurality of bytes includes realigning second bytes of the plurality of bytes in the burst buffer, and

wherein transferring the realigned plurality of bytes to the second memory includes transmitting the realigned second bytes to the second memory.

17. A system including a controller programmed to perform the method of claim 14 .

18. The method of claim 8 , comprising

discarding first bytes of the plurality of bytes, and

wherein realigning the plurality of bytes in one or more second frames of the burst buffer includes realigning second bytes of the plurality of bytes in one or more second frames of the burst buffer.

19. The method of claim 1 , comprising

reading third bytes of the plurality of bytes from the first memory after realigning the second bytes in the burst buffer,

realigning the third bytes in the burst buffer prior to transferring the realigned second bytes from the burst buffer to the second memory, and

transferring the realigned second bytes and the realigned third bytes from the burst buffer to the second memory.

20. The method of claim 1 , comprising

reading a first beat including the first bytes and the second bytes from the first memory,

discarding the first bytes of the plurality of bytes,

realigning the second bytes of the plurality of bytes in the burst buffer,

reading a second beat including third bytes from the first memory,

realigning the third bytes of the plurality of bytes in the burst buffer,

determining that all beats have been read from the first memory, and

transferring the realigned second bytes and the realigned third bytes from the burst buffer to the second memory.

Assignments (2)
SECURITY INTEREST Recorded Jan 14, 2025
From: HUGHES NETWORK SYSTEMS, LLC
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 069862/0464 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2022
From: DANDA, ANEESHWAR; LAGER, ROBERT H.; VEMURI, SAHITHI
To: HUGHES NETWORK SYSTEMS, LLC
Reel/Frame 061254/0090 →