Error check and scrub for semiconductor memory device
Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.
1. A memory device comprising:
a memory array including a bank of memory cells;
an error-correction code (ECC) circuit coupled with the memory array; and
circuitry coupled with the memory array and the ECC circuit, the circuitry configured to:
receive, from a host device, a first refresh command directed to the bank of memory cells;
in response to receiving the first refresh command, retrieving data from a target row of the bank of memory cells, the data comprising a code word corresponding to an address associated with the target row;
detecting at least one error in the code word using the ECC circuit;
receiving, at the memory device, a second refresh command directed to the bank of memory cells; and
in response to receiving the second refresh command, writing at the address the code word with the at least one error corrected.
2. The memory device of claim 1 , wherein the circuitry is further configured to correct the at least one error in the code word using the ECC circuit based at least in part on detecting the at least one error.
3. The memory device of claim 2 , wherein the circuitry is further configured to write a register with an indication that the code word has been corrected based on correcting the at least one error in the code word.
4. The memory device of claim 1 , wherein the circuitry is further configured to write the data that include the code word with the at least one error corrected in one or more registers coupled with the bank of memory cells.
5. The memory device of claim 4 , wherein the one or more registers are configured to have a data dimension corresponding to a first number of bits in the code word and a second number of bits in a parity field associated with the code word.
6. The memory device of claim 1 , wherein the circuitry is further configured to determine whether one or more write commands have been executed to the address.
7. The memory device of claim 1 , wherein the circuitry is further configured to maintain a scrub list of addresses based upon a performance characteristic of the addresses, and to select the target row from the scrub list in response to the first refresh command.
8. A method comprising:
receiving, at a memory device, a first refresh command directed to a bank of memory cells;
retrieving, in response to receiving the first refresh command, data from a target row of the bank, the data comprising a code word corresponding to an address associated with the target row;
detecting at least one error in the code word of the retrieved data;
receiving, at the memory device, a second refresh command directed to the bank of memory cells; and
writing at the address, in response to receiving the second refresh command, the code word with the at least one error corrected.
9. The method of claim 8 , further comprising:
deactivating the target row of the bank of memory cells before receiving, at the memory device, the second refresh command.
10. The method of claim 8 , further comprising:
correcting the at least one error in the code word based at least in part on detecting the at least one error, wherein detecting and correcting the at least one error in the code word comprises using an error-correction code (ECC) circuit of the memory device.
11. The method of claim 10 , further comprising:
writing to a register an indication that the code word has been corrected based on correcting the at least one error in the code word.
12. The method of claim 8 , further comprising:
writing the data that include the code word with the at least one error corrected in one or more registers coupled with the bank of memory cells.
13. The method of claim 8 , further comprising:
determining that a write command has not been executed to the address, wherein writing at the address the code word with the at least one error corrected is based on the determination.
14. A method comprising:
receiving, at a memory device, a first refresh command directed to a bank of memory cells that includes a plurality of rows; and
in response to receiving the first refresh command:
retrieving a first code word from a first row of the plurality of rows, the first code word corresponding to an address associated with the first row; and
checking for one or more errors in the first code word using an error-correction code (ECC) circuit of the memory device.
15. The method of claim 14 , further comprising:
correcting at least one error in the first code word; and
storing the first code word with the at least one error corrected in one or more registers coupled with the bank of memory cells.
16. The method of claim 14 , further comprising:
receiving, at the memory device, a second refresh command directed to the bank of memory cells; and
in response to receiving the second refresh command:
determining that the first code word includes no error;
retrieving a second code word from the second row; and
checking for one or more errors in the second code word using the ECC circuit.
17. The method of claim 14 , further comprising:
correcting at least one error in the first code word using the ECC circuit when the ECC circuit detects the at least one error based on checking for the one or more errors in the first code word; and
setting an indication that the first code word has been corrected.
18. The method of claim 17 , further comprising:
receiving, at the memory device, a second refresh command directed to the bank of memory cells; and
in response to receiving the second refresh command:
writing at the address, based at least in part on the indication, the first code word with the at least one error corrected.
19. The method of claim 18 , further comprising:
determining that a write command has not been executed at the address, wherein writing at the address the first code word with the at least one error corrected is based on the determination.
20. The method of claim 17 , further comprising:
receiving, at the memory device, a second refresh command directed to the bank of memory cells; and
in response to receiving the second refresh command:
determining that at least one write command has been executed at the address;
retrieving a second code word from the second row; and
checking for one or more errors in the second code word using the ECC circuit.