Memory system and method for controlling nonvolatile memory with a host memory buffer

1. A memory system connectable to a host, the memory system comprising:

a nonvolatile memory including a plurality of blocks; and

a controller electrically connected to the nonvolatile memory and configured to control the nonvolatile memory, wherein

the controller is configured to:

receive from the host a write command to designate storage location information indicative of a storage location in a write buffer of the host where write data is stored, the write buffer of the host existing in the host;

retrieve the write data from the write buffer of the host, based on the storage location information;

execute a write operation of writing the write data to a write destination location of a write destination block selected from the plurality of blocks;

in a case that a first read command to designate the write data as read target data is received from the host before the write operation is finished such that the write data becomes readable from the nonvolatile memory, execute a read operation including an operation of reading the read target data from the write buffer of the host and an operation of returning the read target data to the host; and

in a case that read target data designated by the first read command received from the host is readable from the write destination block and the read target data exists in the write buffer of the host, delay issuing a write buffer release request to the host until execution of the first read command is completed, the write buffer release request being a request releasing a region in the write buffer where the write data is stored.

2. The memory system of claim 1 , wherein

the controller is configured to transmit to the host the release request after execution of the first read command is completed.

3. The memory system of claim 1 , wherein

the controller is configured to, in a case that the read target data designated by the first read command received from the host is readable from the write destination block and the read target data exists in the write buffer of the host, execute a read operation including an operation of reading the read target data from the write buffer and an operation of returning the read target data to the host.

4. The memory system of claim 1 , wherein

the write operation of the write data is executed by plural write steps including transferring the write data to the nonvolatile memory at plural times, and

the controller is configured to:

set a first counter value to a value obtained by adding 1 to a number of times of the write steps necessary to the write operation;

decrement the first counter value by 1 every time one write step is finished;

decrement the first counter value by 1 when the write operation is finished such that the write data becomes readable;

increment the first counter value by 1 when receiving the first read command during execution of the write operation;

decrement the first counter value by 1 when the read operation is finished; and

transmit to the host a release request to release the region in the write buffer where the write data is stored when the first counter value becomes zero.

5. A method of controlling a nonvolatile memory including a plurality of blocks, the method comprising:

receiving from a host a write command to designate storage location information indicative of a storage location in a write buffer of the host where write data is stored, the write buffer of the host existing in the host;

retrieving the write data from the write buffer of the host, based on the storage location information;

executing a write operation of writing the write data to a write destination location of a write destination block selected from the plurality of blocks;

in a case that a first read command to designate the write data as read target data is received from the host before the write operation is finished such that the write data becomes readable from the nonvolatile memory, executing a read operation including an operation of reading the read target data from the write buffer of the host and an operation of returning the read target data to the host; and

in a case that read target data designated by the first read command received from the host is readable from the write destination block and the read target data exists in the write buffer of the host, delaying transmitting a write buffer release request to the host until execution of the first read command is completed, the write buffer release request being a request releasing a region in the write buffer where the write data is stored.

6. The method of claim 5 , further comprising:

transmitting to the host the write buffer release request after the execution of the first read command is completed.

7. The method of claim 5 , further comprising:

in a case that the read target data designated by the first read command received from the host is readable from the write destination block and the read target data exists in the write buffer, executing a read operation including an operation of reading the read target data from the write buffer and an operation of returning the read target data to the host.

8. The method of claim 5 , wherein

the write operation of the write data is executed by plural write steps including transferring the write data to the nonvolatile memory at plural times, and

the method further comprises:

setting a first counter value to a value obtained by adding 1 to a number of times of the write steps necessary to the write operation;

decrementing the first counter value by 1 every time one write step is finished;

decrementing the first counter value by 1 when the write operation is finished such that the write data becomes readable;

incrementing the first counter value by 1 when receiving the first read command during execution of the write operation;

decrementing the first counter value by 1 when the read operation is finished; and

transmitting to the host a release request to release the region in the write buffer where the write data is stored when the first counter value becomes zero.