Insole XYZ force detection system
A low power force detection system includes variable capacitors, a drive sense module, and a processing module. A drive sense circuit of the drive sense module is operable to provide an analog and frequency domain signal to a variable capacitor. The drive sense circuit is further operable to detect a characteristic of the variable capacitor based on the analog and frequency domain signal and to generate a representative signal of the characteristic. The processing module is operable to generate a digital value based on the representative and to write the digital value to memory.
1. A low power force detection system comprises:
a plurality of variable capacitors, wherein a variable capacitor of the plurality of variable capacitors includes:
two plates;
one or more conductive layers; and
one or more insulating layers when the variable capacitor includes more than one conductive layer;
a drive sense module operably coupled to the plurality of variable capacitors, wherein a drive sense circuit of the drive sense module is coupled to one or more variable capacitors of the plurality of capacitors, and wherein the drive sense circuit is operable to:
provide an analog and frequency domain signal to the one or more variable capacitors;
detect a characteristic of the one or more variable capacitors based on the analog and frequency domain signal; and
generate a representative signal of the characteristic; and
a processing module operable to the drive sense module, wherein the processing module is operable to:
generate a digital value based on the representative; and
write the digital value to memory.
2. The low power force detection system of claim 1 , wherein the analog and frequency domain signal comprises:
a DC signal component; and
an oscillating signal component that has a frequency and a magnitude.
3. The low power force detection system of claim 1 , wherein the characteristic comprises:
an impedance based on a current and a voltage, wherein one of the current and the voltage is regulated and the other is a reference.
4. The low power force detection system of claim 1 further comprises:
the drive sense circuit being including:
an operational amplifier operable to generate an analog signal representing impedance of the one or more variable capacitors; and
an analog to digital converter operable to generate the representative signal as an unfiltered digital representation of the representing impedance of the one or more variable capacitors;
the processing module being further operable to:
digitally filter the representative signal to produce a high-resolution digital value of the impedance of the one or more variable capacitors.
5. The low power force detection system of claim 1 further comprises:
a clock circuit operable to generate a sampling clock and a digital clock, wherein a sampling rate for sampling impedance of the one or more variable capacitors is derived from the sampling clock and wherein the writing the digital value to the memory is done a write rate that is derived from the digital clock.
6. The low power force detection system of claim 5 , wherein the clock circuit is further operable to:
generate a real-time clock, wherein the processing module time stamps the digital value in accordance with the real-time clock as part of writing the digital value to the memory.
7. The low power force detection system of claim 1 further comprises:
a communication circuit operably coupled to the processing module and to the memory, wherein the communication circuit communicates with a computing entity to download stored digital values to the computing entity.
8. The low power force detection system of claim 1 further comprises:
a power source circuit operable to provide power to the low power force detection system, wherein the power source circuit includes one or more of:
a battery;
a battery charger;
a linear regulator;
a power supply; and
a power harvesting circuit.
9. The low power force detection system of claim 1 , wherein the processing module is further operable to generate the digital value by:
converting the representative signal of the characteristic into an impedance value as the digital value.
10. The low power force detection system of claim 1 , wherein the processing module is further operable to generate the digital value by:
converting the representative signal of the characteristic into an impedance value; and
converting the impedance value into a capacitance value as the digital value.
11. The low power force detection system of claim 1 , wherein the processing module is further operable to generate the digital value by:
converting the representative signal of the characteristic into an impedance value;
converting the impedance value into a capacitance value; and
converting the capacitance value into a pressure value as the digital value.
12. A low power force detection system comprises:
a plurality of pressure sensor cells arranged in a pattern within a sole of a shoe, wherein a pressure sensor cell of the plurality of pressure sensor cells includes a set of variable capacitors, wherein a variable capacitor of the set of variable capacitors includes:
two plates;
one or more conductive layers; and
one or more insulating layers when the variable capacitor includes more than one conductive layer;
a plurality of drive sense modules operably coupled to the plurality of pressure sensor cells, wherein a drive sense module of the plurality of drive sense modules includes a set of drive sense circuits, wherein a drive sense circuit of the set of drive sense circuits is coupled to a variable capacitor of the set of variable capacitors, and wherein the drive sense circuit is operable to:
provide an analog and frequency domain signal to the variable capacitor;
detect a characteristic of the variable capacitor based on the analog and frequency domain signal; and
generate a representative signal of the characteristic; and
a processing module operable to the drive sense module, wherein the processing module is operable to:
generate a digital value based on the representative; and
write the digital value to memory.
13. The low power force detection system of claim 12 , wherein the pattern comprises:
the plurality of pressure sensor cells distributed substantially evenly throughout the sole from a top view perspective, wherein the plurality of pressure sensor cells is of approximately equal size.
14. The low power force detection system of claim 12 , wherein the pattern comprises:
the plurality of pressure sensor cells arranged in a toe zone, a ball of foot zone, a later midfoot zone, and a heal zone, wherein, within one of the zones, the pressure sensor cells are of approximately equal size.
15. The low power force detection system of claim 12 , wherein the pattern comprises:
a first set of a first size pressure sensor cells in a toe area of the shoe;
a second set of a second size pressure sensor cells in a ball of foot area of the shoe; and
a third set of a third size pressure sensor cells in a heal area of the shoe, wherein the second size is greater than the third size, which is greater than the first size.
16. The low power force detection system of claim 12 further comprises:
the drive sense circuit being including:
an operational amplifier operable to generate an analog signal representing impedance of the variable capacitor; and
an analog to digital converter operable to generate the representative signal as an unfiltered digital representation of the representing impedance of the variable capacitor;
the processing module being further operable to:
digitally filter the representative signal to produce a high-resolution digital value of the impedance of the variable capacitor.
17. The low power force detection system of claim 12 further comprises:
a clock circuit operable to generate a sampling clock and a digital clock, wherein a sampling rate for sampling impedance of the variable capacitor is derived from the sampling clock and wherein the writing the digital value to the memory is done a write rate that is derived from the digital clock.
18. The low power force detection system of claim 17 , wherein the clock circuit is further operable to:
generate a real-time clock, wherein the processing module time stamps the digital value in accordance with the real-time clock as part of writing the digital value to the memory.
19. The low power force detection system of claim 12 further comprises:
a communication circuit operably coupled to the processing module and to the memory, wherein the communication circuit communicates with a computing entity to download stored digital values to the computing entity.
20. The low power force detection system of claim 12 further comprises:
a power source circuit operable to provide power to the low power force detection system, wherein the power source circuit includes one or more of:
a battery;
a battery charger;
a linear regulator;
a power supply; and
a power harvesting circuit.
21. The low power force detection system of claim 12 , wherein the processing module is further operable to generate the digital value by:
converting the representative signal of the characteristic into an impedance value as the digital value.
22. The low power force detection system of claim 12 , wherein the processing module is further operable to generate the digital value by:
converting the representative signal of the characteristic into an impedance value; and
converting the impedance value into a capacitance value as the digital value.
23. The low power force detection system of claim 12 , wherein the processing module is further operable to generate the digital value by:
converting the representative signal of the characteristic into an impedance value;
converting the impedance value into a capacitance value; and
converting the capacitance value into a pressure value as the digital value.