Magnetoresistive asymmetry compensation

1. An apparatus comprising:

a digital magnetoresistive asymmetry (MRA) compensation circuit configured to:

receive, from an analog-to-digital converter (ADC), a digital sample sequence corresponding to an analog signal;

perform digital MRA compensation on the digital sample sequence;

output an MRA-compensated sample sequence; and

a digital backend (DBE) configured to produce a bit sequence corresponding to the analog signal based on the MRA-compensated sample sequence.

2. The apparatus of claim 1 further comprising:

an analog front end (AFE) configured to:

receive an original analog signal;

generate the analog signal by adjusting a dynamic range of the original analog signal to correspond to an input range of the ADC; and

provide the analog signal to the ADC.

3. The apparatus of claim 2 , wherein generating the analog signal includes:

perform analog MRA compensation to compensate for a fixed value of MRA in the original analog signal, the fixed value being fixed during read operations and adjustable in-between read operations.

4. The apparatus of claim 2 , wherein generating the analog signal includes:

perform analog offset compensation to constrain an extremum of the original analog signal, rather than to modify the original analog signal to have a zero mean.

5. The apparatus of claim 4 further comprising:

an offset estimation circuit configured to:

receive the digital sample sequence from the ADC;

compare a sample from the digital sample sequence to a threshold value; and

send a control signal to the AFE to adjust an amount of analog offset compensation applied to the analog signal based on the sample exceeding the threshold value.

6. The apparatus of claim 5 further comprising:

a DBE subsystem configured to process digital samples that include MRA, the DBE subsystem configured to receive the digital sample sequence from the ADC that is not processed by the digital MRA compensation circuit;

the digital backend configured to produce the bit sequence based on:

the MRA-compensated sample sequence from the digital MRA compensation circuit; and

output from the DBE subsystem.

7. The apparatus of claim 5 further comprising:

a digital offset compensation circuit configured to:

receive the digital sample sequence from the ADC;

generate a digital offset-compensated sample sequence by adjusting the digital sample sequence to have a zero mean; and

the digital MRA compensation circuit further configured to generate the MRA-compensated sample sequence based on the digital offset-compensated sample sequence.

8. A method comprising:

receiving, at a digital magnetoresistive asymmetry (MRA) compensation circuit from an analog-to-digital converter (ADC), a digital sample sequence corresponding to an analog signal;

performing digital MRA compensation on the digital sample sequence at the digital MRA compensation circuit;

outputting an MRA-compensated sample sequence from the digital MRA compensation circuit; and

producing, at a digital backend (DBE), a bit sequence corresponding to the analog signal based on the MRA-compensated sample sequence.

9. The method of claim 8 further comprising:

receiving an original analog signal at an analog front end (AFE);

generating the analog signal at the AFE by adjusting a dynamic range of the original analog signal to correspond to an input range of the ADC; and

providing the analog signal from the AFE to the ADC.

10. The method of claim 9 , wherein generating the analog signal includes:

performing analog MRA compensation to compensate for a fixed value of MRA in the original analog signal, the fixed value being fixed during read operations and adjustable in-between read operations.

11. The method of claim 9 further comprising:

generating the analog signal includes performing analog offset compensation to constrain an extremum of the original analog signal, rather than to modify the original analog signal to have a zero mean;

receiving the digital sample sequence from the ADC at an offset estimation circuit;

comparing a sample from the digital sample sequence to a threshold value at the offset estimation circuit; and

sending a control signal from the offset estimation circuit directing the AFE to adjust an amount of analog offset compensation applied to the analog signal based on the sample exceeding the threshold value.

12. The method of claim 8 further comprising:

processing digital samples that include MRA at a digital backend (DBE) subsystem configured to receive the digital sample sequence from the ADC that is not processed by the digital MRA compensation circuit;

producing a bit sequence at the DBE based on:

the MRA-compensated sample sequence from the digital MRA compensation circuit; and

output from the DBE subsystem.

13. The method of claim 8 further comprising:

receiving the digital sample sequence from the ADC at a digital offset compensation circuit;

generating, at the digital offset compensation circuit, a digital offset-compensated sample sequence by adjusting the digital sample sequence to have a zero mean; and

generating, at the digital MRA compensation circuit, the MRA-compensated sample sequence based on the digital offset-compensated sample sequence.

14. An apparatus comprising:

a continuous time front end (CTFE) configured to:

receive an original analog signal;

generate an analog signal by adjusting a dynamic range of the original analog signal to correspond to an input range of an analog-to-digital converter (ADC);

provide the analog signal to the ADC;

the ADC configured to convert the analog signal to a digital sample sequence;

a digital magnetoresistive asymmetry (MRA) compensation circuit configured to:

receive the digital sample sequence from the ADC;

perform digital MRA compensation on the digital sample sequence; and

output an MRA-compensated sample sequence.

15. The apparatus of claim 14 further comprising:

the CTFE further configured to:

generate the adjusted analog signal by performing analog MRA compensation for a fixed value of MRA in the analog signal, the fixed value being fixed during read operations and adjustable in-between read operations; and

adjust the fixed value based on an amount of digital MRA compensation applied by the digital MRA compensation circuit.

16. The apparatus of claim 14 further comprising:

the CTFE configured to generate the analog signal by performing analog offset compensation to constrain an extremum of the original analog signal, rather than to modify the original analog signal to have a zero mean;

an offset estimation circuit configured to:

receive the digital sample sequence from the ADC;

compare a sample from the digital sample sequence to a threshold value; and

send a control signal to the AFE to adjust an amount of analog offset compensation applied to the analog signal based on the sample exceeding the threshold value.

17. The apparatus of claim 14 further comprising:

a digital backend (DBE) subsystem configured to process digital samples that include MRA, the DBE subsystem configured to receive the digital sample sequence from the ADC that is not processed by the digital MRA compensation circuit;

a DBE configured to produce a bit sequence based on:

the MRA-compensated sample sequence from the digital MRA compensation circuit; and

output from the DBE subsystem.

18. The apparatus of claim 14 further comprising:

a digital backend (DBE) configured to produce a bit sequence corresponding to the analog signal based on the MRA-compensated sample sequence.

19. The apparatus of claim 7 further comprising:

a DBE subsystem configured to process digital samples that include MRA, the DBE subsystem configured to receive the digital offset-compensated sample sequence from the digital offset compensation circuit without the digital offset-compensated sample sequence having been processed by the digital MRA compensation circuit; and

the DBE configured to produce the bit sequence based on:

the MRA-compensated sample sequence from the digital MRA compensation circuit; and

output from the DBE subsystem.

20. The method of claim 13 further comprising:

processing digital samples that include MRA at a digital backend (DBE) subsystem configured to receive the digital offset-compensated sample sequence from the digital offset compensation circuit without the digital offset-compensated sample sequence having been processed by the digital MRA compensation circuit; and

producing a bit sequence at the DBE based on:

the MRA-compensated sample sequence from the digital MRA compensation circuit; and

output from the DBE subsystem.