STACKED MEMORY ROUTING TECHNIQUES
Techniques for signal routing between a host and dynamic random-access memory (DRAM) are provided. In an example, a routing layer for a dynamic random-access memory die (DRAM can include multiple through silicon via (TSV) terminations configured to electrically couple with TSVs of the DRAM, an intermediate interface area, and multiple routing traces. the multiple TSV terminations can be arranged in multiple TSV areas. The multiple TSV areas can be arranged in two columns. The intermediate interface area can include multiple micro-pillar bump terminations configured to couple, via a micro-pillar bump, with corresponding micro-pillar bump terminations of a semiconductor interposer. The multiple routing traces can couple control TSV terminations of the multiple TSV areas with a corresponding micro-pillar bump termination of the intermediate interface.
1 . A routing layer for a dynamic random-access memory die (DRAM), the routing layer comprising:
multiple through silicon via (TSV) terminations configured to electrically couple with TSVs of the DRAM, the multiple TSV terminations arranged in multiple TSV areas, the multiple TSV areas arranged in two columns;
an intermediate interface area including multiple micro-pillar bump terminations configured to couple, via a micro-pillar bump, with corresponding micro-pillar bump terminations of a semiconductor interposer, the intermediate interface area arranged between the two columns and also located between two adjacent TSV areas, of the multiple TSV areas, within one column of the two columns; and
multiple routing traces coupling each control TSV termination of the two adjacent TSV areas with a corresponding micro-pillar bump termination of the intermediate interface.