IP Library Granted Patent US 12,068,366
Granted Patent B2
US 12,068,366 · App. 17/587,753 · Granted Aug 20, 2024

Semiconductor device

Inventor: Tomohiro Moriya (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/063H01L21/0465H01L21/7602H01L21/761H01L29/0623H01L29/1095H01L29/1608H01L29/66068H01L29/7811H01L29/7813
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Quick Facts
Patent No.
US 12,068,366
App. No.
17/587,753
Granted
Aug 20, 2024
Kind
B2
Abstract

A semiconductor device includes n-type drift layer, n-type current spreading layer having higher impurity concentration than the drift layer, p-type base region provided on top surface, p-type gate-bottom protection region located in the current spreading layer, having first bottom edge portion formed of curved surface, p-type base-bottom embedded region in contact with bottom surface of the base region, having second bottom edge portion formed of curved surface on side surface facing the gate-bottom protection region, being separated from the gate-bottom protection region, and insulated gate electrode structure provided in trench penetrating through the base region to reach the gate-bottom protection region. Bottom surface of the base-bottom embedded region is deeper than bottom surface of the gate-bottom protection region, and minimum value of curvature radius of the first bottom edge portion is larger than minimum value of curvature radius of the second bottom edge portion.

Claims (17)

1. A semiconductor device comprising:

a drift layer of a first conductivity type made of a hexagonal semiconductor having a wider bandgap than silicon;

a current spreading layer of the first conductivity type disposed on a top surface of the drift layer, having a higher impurity concentration than the drift layer;

a base region of a second conductivity type disposed on a top surface of the current spreading layer;

a gate-bottom protection region of the second conductivity type located in the current spreading layer, having a first bottom edge portion formed of a curved surface;

a base-bottom embedded region of the second conductivity type in contact with a bottom surface of the base region while being separated from the gate-bottom protection region in the current spreading layer, the base-bottom embedded region having a second bottom edge portion formed of a curved surface on a side surface facing the gate-bottom protection region; and

an insulated-gate electrode structure provided in a trench penetrating the base region to reach the gate-bottom protection region,

wherein in a cross section perpendicularly cut to an extending direction of the trench,

a bottom surface of the base-bottom embedded region is placed deeper than a bottom surface of the gate-bottom protection region, and

a minimum value of a curvature radius of the first bottom edge portion is larger than a minimum value of a curvature radius of the second bottom edge portion.

2. The semiconductor device of claim 1 , wherein the gate-bottom protection region has a higher impurity concentration than the base-bottom embedded region.

3. The semiconductor device of claim 1 , wherein the gate-bottom protection region has an impurity concentration of 3×10 18 cm −3 or more and less than 1×10 19 cm −3 .

4. The semiconductor device of claim 1 , wherein the base-bottom embedded region has an impurity concentration of 1×10 17 cm −3 or more and less than 3×10 18 cm −3 .

5. The semiconductor device of claim 1 , wherein the gate-bottom protection region has a top edge portion formed of a curved surface, and a minimum value of a curvature radius of the top edge portion is larger than the minimum value of the curvature radius of the second bottom edge portion.

6. The semiconductor device of claim 1 , further comprising a local current spreading layer of the first conductivity type in contact with a bottom surface of the base-bottom embedded region, having a higher impurity concentration than the current spreading layer.

7. The semiconductor device of claim 1 , further comprising a guard ring of the second conductivity type disposed around an active area where the insulated-gate electrode structure is provided, a bottom surface of the guard ring being located at the same depth level as the bottom surface of the base-bottom embedded region on the drift layer, and the guard ring has the same impurity concentration as the base-bottom embedded region.

8. The semiconductor device of claim 1 , wherein the hexagonal semiconductor is silicon carbide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2022
From: MORIYA, TOMOHIRO
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 058814/0540 →
Priority Claims (1)
JP 2021-058100 · Mar 30, 2021 · national
Continuity (1)
Related Publication 20220320268A1 · Oct 6, 2022