Multicore shared cache operation engine

1. A system comprising:

a processor;

one or more memories; and

a memory controller having a plurality of control channels including a first control channel, wherein the first control channel is configured to:

receive configuration information defining a trigger event;

receive a memory command to perform a memory operation;

detect the trigger event; and

responsive to the detection of the trigger event, transmit the memory command to perform the memory operation.

2. The system of claim 1 , comprising a first interface and a second interface, wherein the memory command is received from a selected one of the first interface or the second interface, the selection of the first interface or the second interface being based on the configuration information.

3. The system of claim 2 , wherein:

the first interface is a system bus coupled to the memory controller and the memory command is received as a message on the system bus when the first interface is selected by the first control channel based on the configuration information; and

the second interface is an interface to a memory mapped register and the memory command is written to the memory mapped register when the second interface is selected by the first control channel based on the configuration information.

4. The system of claim 3 , wherein the system bus is a packet streaming interface link bus.

5. The system of claim 1 , comprising a first channel configuration register associated with the first control channel, wherein the configuration information received by the first control channel is first written to the first channel configuration register.

6. The system of claim 5 , wherein the first channel configuration register is one of a plurality of channel configuration registers, and wherein each of the plurality of control channels is associated with a respective one of the channel configuration registers.

7. The system of claim 1 , wherein the one or more memories includes at least a first memory and a second memory.

8. The system of claim 7 , wherein the first memory is a memory that is external to the processor and the memory controller and the second memory is a cache memory, wherein the memory command is a command to transfer data from the first memory to the second memory.

9. The system of claim 8 , wherein the external memory is a dynamic random-access memory (DRAM).

10. The system of claim 8 , wherein the cache memory is a level one (L1) or a level two (L2) cache.

11. The system of claim 10 , wherein the processor comprises a plurality of processing cores, and wherein the cache memory is an L2 cache shared by the plurality of processing cores.

12. The system of claim 1 , wherein the configuration information defines the trigger event as one of a global event or a local event.

13. The system of claim 12 , comprising:

a system bus coupling to the memory controller; and

a local bus coupled to the first control channel;

wherein:

when the trigger event is defined as a global event, the trigger event is an event indicated using the system bus; and

when the trigger event is defined as a local event, the trigger event is an event indicated using the local bus.

14. A method comprising:

configuring a control channel of a memory controller to detect a trigger event and to receive a memory command;

after receiving the memory command, detect the trigger event; and

responsive to detecting the trigger event, transmit a memory command from the control channel to cause a memory operation to be performed.

15. The method of claim 14 , wherein configuring the control channel to receive the memory command comprises configuring the control channel to select one of a first interface or a second interface and to receive the memory command using the selected one of the first interface or the second interface.

16. The method of claim 15 , wherein the first interface is a system bus coupled to the memory controller and the control channel receives the memory command as a message on the system bus when the first interface is selected, and wherein the second interface is an interface to a memory mapped register and the control channel receives the memory command from the memory mapped register when the second interface is selected.

17. The method of claim 14 , wherein the trigger event is one a global event or a local event, wherein, when the trigger event is a global event, the trigger event is an event indicated to the control channel using a system bus and, wherein, when the trigger event is defined as a local event, the trigger event is an event indicated to the control channel using a local bus.

18. A system comprising:

a first interface;

a second interface;

a first channel configuration register;

one or more memories; and

a memory controller having a plurality of control channels including a first control channel associated with the first channel configuration register, wherein the first control channel is configured to:

receive configuration information defining a trigger event;

write the configuration information to the first channel configuration register;

select the first interface or the second interface based on the configuration information;

receive, on the selected interface, a memory command to perform a memory operation;

detect the trigger event; and

transmit the memory command to perform the memory operation in response to detecting of the trigger event.

19. The system of claim 18 ,

wherein the first interface is a system bus coupled to the memory controller,

wherein the memory command is received as a message on the system bus when the first interface is selected by the first control channel based on the configuration information,

wherein the second interface is an interface to a memory mapped register, and

wherein the memory command is written to the memory mapped register when the second interface is selected by the first control channel based on the configuration information.

20. The system of claim 18 , wherein the one or more memories include:

a cache memory; and

a dynamic random-access memory (DRAM) external to the memory controller,

wherein the memory command is a command to transfer data from the DRAM to the cache memory.