Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

1. A memory array, comprising:

laterally-spaced memory blocks, wherein each of the laterally-spaced memory blocks comprises sub-blocks that are defined at least in part by channel openings and laterally-spaced upper select gates and lower select gates on each of the laterally-spaced memory blocks;

an isolation structure that laterally separates immediately adjacent sub-blocks which are defined at least by the laterally-spaced upper select gates;

a dummy channel-material string that extends elevationally above the lower select gates and through the isolation structure;

a vertical stack below the upper select gates having alternating insulative tiers and wordline tiers; and

channel-material strings extending elevationally through the upper select gates and through the insulative tiers and the wordline tiers within the sub-blocks, the channel-material strings having a common horizontal pitch-spacing within individual of the sub-blocks along parallel horizontally-straight lines between longitudinal edges of the individual laterally-spaced memory blocks, the channel-material strings along the parallel horizontally-straight lines being horizontally spaced from one another by the isolation structure between the immediately-adjacent sub-blocks by a distance that is greater than the common horizontal pitch-spacing.

2. The memory array of claim 1 wherein the wordline tiers comprise gate regions of individual memory cells, the gate regions individually comprising part of a wordline in the wordline tiers, the individual laterally-spaced memory blocks being characterized by conducting material of the wordline that extends horizontally continuously from and between the longitudinal edges of the individual laterally-spaced memory blocks.

3. The memory array of claim 1 , wherein the isolation structure extends vertically through the insulative tiers and the wordline tiers within and all along the individual laterally-spaced memory blocks.

4. The memory array of claim 1 wherein the elevationally extending dummy channel-material string is formed in a dummy opening between the immediately adjacent sub-blocks.

5. The memory array of claim 4 wherein no portion of the dummy channel-material string formed in the dummy opening is at the same elevation as the laterally-spaced upper select gates.

6. The memory array of claim 4 wherein the dummy channel-material string includes a maximum horizontal width that is smaller than a maximum horizontal width of individual operative channel-material strings that are formed in the channel openings.

7. The memory array of claim 6 wherein the operative channel-material strings are taller than the dummy channel-material string.

8. The memory array of claim 1 further comprising trenches that facilitate formation of conductive materials in the wordline tiers.

9. The memory array of claim 1 wherein the memory array comprises NAND.

10. A memory array, comprising:

laterally-spaced memory blocks, the memory blocks individually comprising sub-blocks that are defined at least in part by laterally-spaced upper select gates and lower select gates on each of the laterally-spaced memory blocks, wherein an isolation structure laterally separates immediately adjacent sub-blocks which are defined at least by the laterally-spaced upper select gates;

a vertical stack below the upper select gates having alternating insulative tiers and wordline tiers;

operative channel-material strings extending elevationally through the upper select gates and through the insulative tiers and the wordline tiers within the sub-blocks, the operative channel-material strings having a common horizontal pitch-spacing within individual of the sub-blocks along parallel horizontally-straight lines between longitudinal edges of the individual laterally-spaced memory blocks, the operative channel-material strings along the parallel horizontally-straight lines being horizontally spaced from one another by the isolation structure between the immediately-adjacent of the sub-blocks by a distance that is greater than the common horizontal pitch-spacing; and

dummy channel-material string extending elevationally through the isolation structure, upper select gates and into the insulative tiers and the wordline tiers between the sub blocks, the dummy channel material string includes a maximum horizontal width that is smaller than a maximum horizontal width of individual of the operative channel material strings.

11. The memory array of claim 10 , wherein the operative channel-material strings are taller than the dummy channel-material string.

12. The memory array of claim 10 wherein the memory array comprises NAND.

13. A memory array, comprising:

laterally-spaced memory blocks, the memory blocks individually comprising sub-blocks defined at least in part by laterally-spaced upper select gates and laterally-spaced lower select on each of the laterally-spaced memory blocks;

an isolation structure that laterally separates immediately adjacent sub-blocks which are defined at least by the laterally-spaced upper select gates in an upper construction of each of the laterally-spaced memory blocks;

a vertical stack below the upper select gates having alternating insulative tiers and wordline tiers;

operative channel-material strings extending elevationally through the upper select gates and through the insulative tiers and the wordline tiers within the sub-blocks, the operative channel-material strings along parallel horizontally-straight lines being horizontally spaced from one another by the isolation structure between the immediately-adjacent of the sub-blocks by a distance that is greater than a common horizontal pitch-spacing between the operative channel-material strings within individual of the sub-blocks; and

dummy channel-material string that is formed in individual dummy openings between the immediately adjacent and extending elevationally through the isolation structure, upper select gates, and into the insulative tiers and the wordline tiers between the sub-blocks, the operative channel-material strings being taller than the dummy channel-material string.

14. The memory array of claim 13 wherein the memory array comprises NAND.