IP Library Granted Patent US 11,955,402
Granted Patent B2
US 11,955,402 · App. 17/608,888 · Granted Apr 9, 2024

Power semiconductor component and method for producing a power semiconductor component

Inventors: Christina Quest-Matt (Munich, DE); Detlev Bagung (Munich, DE); Daniela Wolf (Munich, DE)
Assignee: Vitesco Technologies GbmH
H01L23/3677H01L21/4871H01L24/13H01L24/27H01L24/32H01L24/73H01L24/83H01L2224/09519H01L2224/1319H01L2224/26152H01L2224/27011H01L2224/32225H01L2224/73204H01L2224/83104
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Quick Facts
Patent No.
US 11,955,402
App. No.
17/608,888
Granted
Apr 9, 2024
Kind
B2
Abstract

A power semiconductor component is specified, having a power semiconductor device arranged within a housing, wherein a heat sink is exposed on a first surface of the housing; a wiring substrate which receives the housing with the power semiconductor device and which has a first main surface and a second main surface. A heat dissipation region with increased thermal conductivity is arranged on the second main surface. The housing is arranged on the wiring substrate in such a way that the heat sink is connected to the heat dissipation region via a solder layer. A number of spacers which are arranged between the heat sink and the heat dissipation region are embedded in the solder layer. Furthermore, a method for producing a power semiconductor component is specified.

Claims (12)

1. A power semiconductor component, comprising:

a power semiconductor device arranged within a housing;

a heat sink exposed on a first surface of the housing; a wiring substrate which receives the housing with the power semiconductor device and which has a first main surface and a second main surface;

a heat dissipation region arranged on the second main surface, wherein the housing is arranged on the wiring substrate in such a way that the heat sink is connected to the heat dissipation region via a solder layer;

a number of spacers arranged between the heat sink and the heat dissipation region, wherein the number of spacers are embedded in the solder layer, wherein the spacers are formed from a surface mount device (“SMD”) adhesive, wherein the SMD adhesive comprises an electrically conductive adhesive based on epoxy resin; and

a number of vias arranged in the wiring substrate, wherein the number of vias are configured to introduce solder material between the heat sink and the heat dissipation region of the wiring substrate.

2. The power semiconductor component as claimed in claim 1 , wherein the power semiconductor device arranged in the housing is designed to be through-hole-mountable.

3. The power semiconductor component as claimed in claim 1 , wherein the power semiconductor device arranged in the housing is designed to be surface-mountable.

4. The power semiconductor component as claimed in claim 1 , wherein the housing with the power semiconductor device is electrically connected to the heat dissipation region by means of the spacers and by means of a solder layer.

5. The power semiconductor component as claimed in claim 1 , wherein the heat sink has an area a on the first surface and the heat dissipation region has an area A on the second main surface, where a <A applies.

6. The power semiconductor component as claimed in claim 1 , wherein the heat dissipation region protrudes beyond the housing of the power semiconductor device on all sides.

7. The power semiconductor component as claimed in claim 1 , wherein the heat dissipation region comprises a copper layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2025
From: VITESCO TECHNOLOGIES GMBH
To: SCHAEFFLER TECHNOLOGIES AG & CO. KG
Reel/Frame 072774/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2022
From: QUEST-MATT, CHRISTINA; BAGUNG, DETLEV; WOLF, DANIELA
To: VITESCO TECHNOLOGIES GMBH
Reel/Frame 058906/0688 →
Priority Claims (1)
DE 10 2019 215 503.0 · Oct 10, 2019 · national
Continuity (1)
Related Publication 20220328377A1 · Oct 13, 2022