IP Library Granted Patent US 12,267,012
Granted Patent B2
US 12,267,012 · App. 17/619,397 · Granted Apr 1, 2025

Voltage balance systems and methods for multilevel converters

Inventors: Zheyu Zhang (Clifton Park, NY); Tomas Sadilek (Durham, NC); Ramanujam Ramabhadran (Niskayuna, NY); Hao Tu (Raleigh, NC)
Assignee: GE GRID SOLUTIONS LLC
H02M3/158H02J7/0014H02M1/0025H02J2207/20
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Quick Facts
Patent No.
US 12,267,012
App. No.
17/619,397
Granted
Apr 1, 2025
Kind
B2
Abstract

A multilevel converter system is provided. The system includes a converter and a converter controller interfaced with the converter. The converter controller includes a voltage loop, a current loop, and a voltage compensation loop. The voltage loop is configured to receive first and second voltages from the first and second segments of the converter and a reference voltage. The current loop is configured to receive a current output of the converter, a reference current, and a balancing reference current. The voltage compensation loop is configured to receive the first and second voltages and a sign signal. The converter controller is configured to generate first and second pulse-width modulation (PWM) signals using output signals from the current loop and the output compensation signals from the voltage compensation loop. The PWM signals are configured to control the switches of the converter and to balance the first voltage with the second voltage.

Claims (51)

1. A multilevel converter system comprising:

a converter comprising a first segment and a second segment electrically connected to said first segment, wherein said first and second segments are each configured to convert a first current to a second current, wherein said first segment comprises a plurality of first switches, and wherein said second segment comprises a plurality of second switches;

a balancing reference current generator configured to generate a balancing reference current; and

a converter controller interfaced with said converter, said converter controller comprising:

a voltage loop configured to receive a first voltage from said first segment, a second voltage from said second segment, and a reference voltage, wherein said voltage loop is further configured to generate a reference current;

a current loop configured to:

receive a current output of said converter, the reference current generated by said voltage loop, and the balancing reference current generated by said balancing reference current generator; and

generate output signals based on the current output of said converter, the reference current, and the balancing reference current; and

a voltage compensation loop configured to:

receive the first voltage from said first segment, the second voltage from said second segment, and a sign signal indicating a polarity of the current output of said converter; and

generate output compensation signals based on the first voltage, the second voltage, and the sign signal,

wherein said converter controller is configured to generate first pulse-width modulation (PWM) signals and second PWM signals using the output signals from said current loop and the output compensation signals from said voltage compensation loop, wherein the first PWM signals are configured to control said plurality of first switches, wherein the second PWM signals are configured to control said plurality of second switches, and wherein the first and second PWM signals are configured to balance the first voltage with the second voltage.

2. A multilevel converter system in accordance with claim 1 , wherein the balancing reference current is a sinusoidal alternating current.

3. A multilevel converter system in accordance with claim 1 , wherein the balancing reference current has an amplitude less than 1% of a rated current of said converter.

4. A multilevel converter system in accordance with claim 1 , wherein the balancing reference current has a frequency greater than a control bandwidth of said voltage loop and less than a control bandwidth of said current loop.

5. A multilevel converter system in accordance with claim 1 , wherein said converter comprises one of a symmetric boost multilevel converter and a flying capacitor multilevel converter.

6. A multilevel converter system in accordance with claim 1 , wherein said converter controller is configured to generate first and second duty-cycle functions using the output signals from said current loop and the output compensation signals from said voltage compensation loop, wherein said converter controller comprises a first pulse-width modulator and a second pulse-width modulator, wherein said first pulse-width modulator is configured to generate the first PWM signals using the first duty-cycle function, and wherein said second pulse-width modulator is configured to generate the second PWM signals using the second duty-cycle function.

7. A multilevel converter system in accordance with claim 6 , wherein said current loop comprises a regulator, wherein said current loop is configured to compare the current output of said converter with a sum of the balancing reference current and the reference current generated by said voltage loop and to generate an input to said regulator, and wherein said regulator is configured to generate an output proportional to a sum of the first and second duty-cycle functions.

8. A multilevel converter system in accordance with claim 1 , wherein the sign signal is determined by one of i) sensing the current output of said converter, and ii) summing the reference current generated by said voltage loop and the balancing reference current generated by said balancing reference current generator.

9. A converter controller for a multilevel converter, said converter controller comprising:

a voltage loop configured to receive a first voltage from a first segment of the multilevel converter, a second voltage from a second segment of the multilevel converter, and a reference voltage, wherein said voltage loop is further configured to generate a reference current;

a current loop configured to:

receive a current output from the multilevel converter, a reference current generated by said voltage loop, and a balancing reference current generated by a balancing reference current generator; and

generate output signals based on the current output of the multilevel converter, the reference current, and the balancing reference current; and

a voltage compensation loop configured to:

receive the first and second voltages and a sign signal indicating a polarity of the current output of the multilevel converter; and

generate output compensation signals based on the first and second voltages and the sign signal,

wherein said converter controller is configured to generate first pulse-width modulation (PWM) signals and second PWM signals using the output signals from said current loop and the output compensation signals from said voltage compensation loop, wherein the first PWM signals are configured to control a plurality of first switches of the first segment of the multilevel converter, wherein the second PWM signals are configured to control a plurality of second switches of the second segment of the multilevel converter, and wherein the first and second PWM signals are configured to balance the first voltage with the second voltage.

10. A converter controller in accordance with claim 9 , wherein the balancing reference current is a sinusoidal alternating current.

11. A converter controller in accordance with claim 9 , wherein the balancing reference current has an amplitude less than 1% of a rated current of said multilevel converter.

12. A converter controller in accordance with claim 9 , wherein the balancing reference current has a frequency greater than a control bandwidth of said voltage loop and less than a control bandwidth of said current loop.

13. A converter controller in accordance with claim 9 , further comprising a first pulse-width modulator and a second pulse-width modulator, wherein said converter controller is configured to generate first and second duty-cycle functions using the output signals from said current loop and the output compensation signals from said voltage compensation loop, wherein said first pulse-width modulator is configured to generate the first PWM signals using the first duty-cycle function, and wherein said second pulse-width modulator is configured to generate the second PWM signals using the second duty-cycle function.

14. A converter controller in accordance with claim 9 , wherein the sign signal is determined by one of i) sensing the current output of the converter, and ii) summing the reference current generated by said voltage loop and the balancing reference current generated by the balancing reference current generator.

15. A method of operating a power supply system, said method comprising:

receiving, at a voltage loop of a converter controller, a first voltage from a first segment of a multilevel converter, a second voltage from a second segment of the multilevel converter, and a reference voltage;

generating, by the voltage loop, a reference current;

receiving, at a current loop of the converter controller, a current output from the multilevel converter, the reference current generated by the voltage loop, and a balancing reference current generated by a balancing reference current generator;

generating, by the current loop, output signals based on the current output of the multilevel converter, the reference current, and the balancing reference current;

receiving, at a voltage compensation loop of the converter controller, the first and second voltages and a sign signal indicating a polarity of the current output of the multilevel converter;

generating, by the voltage compensation loop, output compensation signals based on the first and second voltages and the sign signal; and

generating first pulse-width modulation (PWM) signals and second PWM signals using the output signals from the current loop and the output compensation signals from the voltage compensation loop, wherein the first PWM signals are configured to control a plurality of first switches of the first segment of the multilevel converter, wherein the second PWM signals are configured to control a plurality of second switches of the second segment of the multilevel converter, and wherein the first and second PWM signals are configured to balance the first voltage with the second voltage.

16. A method in accordance with claim 15 , further comprising generating, by the balancing reference current generator, the balancing reference current that is a sinusoidal alternating current.

17. A method in accordance with claim 15 , further comprising generating, by the balancing reference current generator, the balancing reference current that has a frequency greater than a control bandwidth of the voltage loop and less than a control bandwidth of the current loop.

18. A method in accordance with claim 15 , further comprising:

setting an amplitude of the balancing reference current to an amplitude greater than 1% of a rated current of the multilevel converter;

adjusting the amplitude of the balancing reference current until the difference between the first and second voltages is within a predetermined threshold; and

decreasing the amplitude of the balancing reference current to an amplitude less than 1% of the rated current of the multilevel converter.

19. A method in accordance with claim 15 , further comprising:

electrically connecting a battery string to the converter; and

electrically connecting the converter to a distribution bus.

20. A method in accordance with claim 15 , further comprising determining the sign signal by one of i) sensing the current output of the converter, and ii) summing the reference current generated by the voltage loop and the balancing reference current generated by the balancing reference current generator.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2023
From: GENERAL ELECTRIC COMPANY
To: GE GRID SOLUTIONS LLC
Reel/Frame 066000/0694 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2021
From: ZHANG, ZHEYU; SADILEK, TOMAS; RAMABHADRAN, RAMANUJAM; TU, HAO
To: GENERAL ELECTRIC COMPANY
Reel/Frame 058397/0908 →
Continuity (1)
Related Publication 20220311337A1 · Sep 29, 2022
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