Planar SiC MOSFET with retrograde implanted channel
A silicon carbide (SiC) planar transistor device includes a SiC semiconductor substrate of a first charge type, a SiC epitaxial layer of the first charge type formed at a top surface of the SiC semiconductor substrate, a source structure of the first charge type formed at a top surface of the SiC epitaxial layer, a drain structure of the first charge type formed at a bottom surface of the SiC semiconductor substrate, a gate structure comprising a gate runner and a gate dielectric that covers at least part of the source structure and the gate runner, and a channel region of a second charge type located in vertical direction below the gate structure and adjacent to the source structure. The channel can be formed by performing a plurality of implantation steps so that the channel region comprises a first region and a second region.
1. A silicon carbide (SiC) planar transistor device comprising:
a SiC semiconductor substrate of a first charge type having a top surface and a bottom surface;
a SiC epitaxial layer of the first charge type formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface;
a source structure of the first charge type formed in the top surface of the SiC epitaxial layer, the source structure having a top surface;
a drain structure of the first charge type formed on the bottom surface of the SiC semiconductor substrate;
a gate structure comprising a gate dielectric and a gate runner, wherein the gate dielectric covers at least part of the source structure and the gate runner;
a channel region of a second charge type located in vertical direction below the gate structure and adjacent to the source structure, wherein a doping profile of the second charge type of the channel region comprises a first region and a second region;
wherein the first region has a constant doping concentration in a range of 2×10 17 cm-3 to 3×10 18 cm −3 and is located in a vertical direction below to the gate dielectric with a depth between 50 nm to 250 nm from the top surface of the SiC epitaxial layer;
wherein the second region has a Pearson-Type-IV-like distributed doping concentration with a peak doping concentration in a range of 1.5×10 8 cm −3 to 8×10 18 cm −3 and is located in a vertical direction below and adjacent to the first region with the peak position of the Pearson-Type-IV-like distribution in a range of 300 nm to 500 nm from the top surface of the SiC epitaxial layer; and
wherein the channel has a length in a range of 50 nm to 250 nm.
2. The silicon carbide planar transistor device according to claim 1 , wherein the planar transistor is a metal-oxide-semiconductor field-effect transistor.
3. The silicon carbide planar transistor device according to claim 2 , wherein the transistor device has threshold voltage in a range of 2V to 3.5V.
4. The silicon carbide planar transistor device according to claim 1 , wherein the planar transistor is an insulated-gate bipolar transistor.
5. The silicon carbide planar transistor device according to claim 4 , wherein the transistor device has threshold voltage in a range of 2V to 3.5V.
6. The silicon carbide planar transistor device according to claim 1 , wherein the transistor device has threshold voltage in a range of 2V to 3.5V.
7. The silicon carbide planar transistor device according to claim 1 , wherein the gate dielectric comprises a gate oxide.
8. The silicon carbide planar transistor device according to claim 1 , wherein an oxide capacitance and interface trap concentration allow for a maximum variation of 2%-5% from a constant value.
9. The silicon carbide planar transistor device according to claim 1 , wherein the first region is doped with Al, N, B or P.
10. A silicon carbide (SiC) planar transistor device comprising:
a SiC semiconductor substrate of a first charge type having a top surface and a bottom surface;
a SiC epitaxial layer of the first charge type formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface;
a source structure of the first charge type formed in the top surface of the SiC epitaxial layer, the source structure having a top surface;
a drain structure of the first charge type formed on the bottom surface of the SiC semiconductor substrate;
a gate structure comprising a gate dielectric and a gate runner, wherein the gate dielectric covers at least part of the source structure and the gate runner;
a channel region of a second charge type located in vertical direction below the gate structure and adjacent to the source structure, wherein a doping profile of the second charge type of the channel region comprises a first region and a second region;
wherein the first region has a constant concentration of dopants in a range of 2×10 17 cm −3 to 3×10 18 cm −3 and is located in a vertical direction below to the gate dielectric with a depth between 50 nm to 250 nm from the top surface of the SiC epitaxial layer, the dopants comprising Al, N, B or P;
wherein the second region has a Pearson-Type-IV-like distributed doping concentration with a peak doping concentration in a range of 1.5×10 18 cm −3 to 8×10 18 cm −3 and is located in a vertical direction below and adjacent to the first region with the peak position of the Pearson-Type-IV-like distribution in a range of 300 nm to 500 nm from the top surface of the SiC epitaxial layer;
wherein the channel has a length in a range of 50 nm to 250 nm; and
wherein the transistor device has threshold voltage in a range of 2V to 3.5V.
11. The silicon carbide planar transistor device according to claim 10 , wherein the planar transistor is a metal-oxide-semiconductor field-effect transistor.
12. The silicon carbide planar transistor device according to claim 10 , wherein the planar transistor is an insulated-gate bipolar transistor.
13. The silicon carbide planar transistor device according to claim 1 , wherein the gate dielectric comprises a gate oxide.