IP Library Granted Patent US 12,176,273
Granted Patent B2
US 12,176,273 · App. 17/645,500 · Granted Dec 24, 2024

Semiconductor device and method of forming substrate with 3-sided wettable flank

Inventors: Henry D. Bathan (Simi Valley, CA); Yingyu Chen (Camarillo, CA)
Assignee: Semtech Corporation
H01L23/49565H01L23/4952H01L23/49548
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Quick Facts
Patent No.
US 12,176,273
App. No.
17/645,500
Granted
Dec 24, 2024
Kind
B2
Abstract

A semiconductor device has a substrate and leads formed on two or more sides of the substrate. An electrical component is disposed over the substrate and electrically connected to the lead with bumps or bond wires. The electrical component is encapsulated. A portion of the substrate is removed to form a wettable flank on at least three sides of the lead. The substrate has a molding compound and the lead is disposed within or adjacent to the molding compound. A portion of the molding compound can remain at corners of the substrate. The lead has a first surface or recessed surface on a first side of the lead, a second surface or recessed surface on a second side of the lead, and a third surface or recessed surface on a third side of the lead. A portion of a surface of the lead is plated.

Claims (43)

1. A semiconductor device, comprising:

a substrate including a first surface and a second surface on a same side of the substrate as the first surface and vertically offset from the first surface;

a lead at least partially embedded in the first surface of the substrate and partially exposed from the substrate over the second surface of the substrate, wherein a top surface of the lead is coplanar with the first surface of the substrate and a width of the lead across the second surface is less than a width of the substrate across the first surface and the lead is exposed from the second surface of the substrate on at least three side surfaces of the lead extending vertically from the first surface of the substrate with a gap extending from one of the at least three side surfaces over the second surface of the substrate to a side surface of the substrate;

an electrical component disposed over the substrate and electrically connected to the lead; and

a wettable flank formed on the at least three side surfaces of the lead.

2. The semiconductor device of claim 1 , wherein the substrate further includes a molding compound and the lead is at least partially embedded in the molding compound.

3. The semiconductor device of claim 2 , wherein a portion of the molding compound remains at corners of the substrate.

4. The semiconductor device of claim 1 , wherein the lead includes a first surface on a first side of the lead, a second surface on a second side of the lead, and a third surface on a third side of the lead.

5. The semiconductor device of claim 1 , wherein the lead includes a first recessed surface on a first side of the lead, a second recessed surface on a second side of the lead, and a third recessed surface on a third side of the lead.

6. The semiconductor device of claim 1 , wherein a portion of a surface of the lead is plated.

7. A semiconductor device, comprising:

a non-conductive substrate including a first surface and a second surface on a same side of the non-conductive substrate as the first surface and vertically offset from the first surface;

an electrical component disposed over the non-conductive substrate;

a lead at least partially embedded in the first surface of the non-conductive substrate and partially exposed from the non-conductive substrate over the second surface of the non-conductive substrate, wherein the lead is exposed from the second surface of the non-conductive substrate on at least three side surfaces of the lead extending vertically from the first surface of the non-conductive substrate with a gap extending from one of the at least three side surfaces over the second surface of the non-conductive substrate to a side surface of the non-conductive substrate; and

a wettable flank formed on the at least three side surfaces of the lead.

8. The semiconductor device of claim 7 , wherein the non-conductive substrate includes a molding compound and the lead is at least partially embedded in the molding compound.

9. The semiconductor device of claim 8 , wherein a portion of the molding compound remains at corners of the non-conductive substrate.

10. The semiconductor device of claim 7 , wherein the lead includes a first surface on a first side of the lead, a second surface on a second side of the lead, and a third surface on a third side of the lead.

11. The semiconductor device of claim 7 , wherein the lead includes a first recessed surface on a first side of the lead, a second recessed surface on a second side of the lead, and a third recessed surface on a third side of the lead.

12. The semiconductor device of claim 7 , wherein a portion of a surface of the lead is plated.

13. The semiconductor device of claim 7 , wherein the leads are formed on two or more sides of the non- conductive substrate.

14. A method of making a semiconductor device, comprising:

providing a non-conductive substrate including a first surface and a second surface on a same side of the non-conductive substrate as the first surface and vertically offset from the first surface;

forming a lead at least partially embedded in the first surface of the non-conductive substrate and partially exposed from the non-conductive substrate over the second surface of the non-conductive substrate, wherein the lead is exposed from the second surface of the non-conductive substrate on at least three side surfaces of the lead extending vertically from the first surface of the non-conductive substrate with a gap extending from one of the at least three side surfaces over the second surface of the non-conductive substrate to a side surface of the non-conductive substrate;

disposing an electrical component over the non-conductive substrate; and

forming a wettable flank on at least three side surfaces of the lead.

15. The method of claim 14 , wherein providing the non-conductive substrate includes:

providing a molding compound; and

embedding the lead at least partially in the molding compound.

16. The method of claim 15 , further including leaving a portion of the molding compound at corners of the non-conductive substrate.

17. The method of claim 14 , wherein the lead includes a first surface on a first side of the lead, a second surface on a second side of the lead, and a third surface on a third side of the lead.

18. The method of claim 14 , wherein the lead includes a first recessed surface on a first side of the lead, a second recessed surface on a second side of the lead, and a third recessed surface on a third side of the lead.

19. The method of claim 14 , further including plating a portion of a surface of the lead.

20. The method of claim 14 , further including forming the leads on two or more sides of the non-conductive substrate.

21. A semiconductor device, comprising:

a substrate including a first surface and a second surface on a same side of the substrate as the first surface and vertically offset from the first surface;

a lead at least partially embedded in the first surface of the substrate and partially exposed from the substrate over the second surface of the substrate, wherein the lead is exposed from the second surface of the substrate on at least three side surfaces of the lead extending vertically from the first surface of the substrate;

an electrical component disposed over the substrate and electrically connected to the lead; and

a wettable flank formed on a plurality of sides of the lead.

22. The semiconductor device of claim 21 , further including a molding compound disposed over the substrate with the lead at least partially embedded in the molding compound.

23. The semiconductor device of claim 22 , wherein a portion of the molding compound remains at corners of the substrate.

24. The semiconductor device of claim 21 , wherein the lead includes a first surface on a first side of the lead, a second surface on a second side of the lead, and a third surface on a third side of the lead.

25. The semiconductor device of claim 21 , wherein the lead includes a first recessed surface on a first side of the lead, a second recessed surface on a second side of the lead, and a third recessed surface on a third side of the lead.

Assignments (2)
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Jan 12, 2023
From: SEMTECH CORPORATION; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 062389/0057 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2022
From: BATHAN, HENRY D.; CHEN, YINGYU
To: SEMTECH CORPORATION
Reel/Frame 058531/0241 →