Semiconductor device and semiconductor die
View Patent ↗A semiconductor device and a semiconductor die are disclosed. The semiconductor device includes: a SPAD wafer containing SPAD dies formed thereon with respective SPAD arrays; a TDC wafer containing TDC dies formed thereon with respective TDC arrays; and a logic wafer containing logic dies formed thereon with respective peripheral logic circuits. The SPAD wafer, TDC wafer and logic wafer are bonded in the sequence set forth. The TDC arrays and peripheral logic circuits are arranged on the TDC and logic wafers, respectively, and the SPAD arrays are bonded to the TDC arrays. The three wafers are bonded and integrated together to form the semiconductor device using a multi-wafer stacking technique. The increased integration of the semiconductor device means an increased fill factor of SPAD arrays for same size, resulting in improved photon detection efficiency of the semiconductor device and improved detection performance of single-photon detectors fabricated from the semiconductor device.
1. A semiconductor device, comprising:
a single-photon avalanche diode (SPAD) wafer containing a plurality of SPAD dies formed thereon with respective SPAD arrays;
a time to digital converter (TDC) wafer containing a plurality of TDC dies formed thereon with respective TDC arrays; and
a logic wafer containing a plurality of logic dies formed thereon with respective peripheral logic circuits,
wherein the SPAD wafer, the TDC wafer and the logic wafer are bonded in the sequence set forth, and wherein each of the plurality of SPAD dies, each of the plurality of TDC dies and each of the plurality of logic dies are sized so as to have a same area.
2. The semiconductor device according to claim 1 , wherein each of the plurality of SPAD dies contains multiple SPADs and each of the plurality of TDC dies contains multiple TDCs, and wherein a number of the SPADs on each SPAD die is equal to a number of the TDCs on each TDC die.
3. The semiconductor device according to claim 2 , wherein each SPAD on each SPAD die occupies an area the same as an area occupied by each TDC on each TDC die.
4. The semiconductor device according to claim 2 , wherein each SPAD on each SPAD die occupies an area different from an area occupied by each TDC on each TDC die.
5. The semiconductor device according to claim 2 , wherein:
the SPAD wafer comprises a first semiconductor layer containing SPAD arrays;
the TDC wafer comprises a second semiconductor layer containing the TDC arrays; and
the SPAD arrays are formed in a portion of the first semiconductor layer close to the TDC dies on the TDC wafer, and each SPAD is configured to receive photons from the side of the first semiconductor layer away from the TDC wafer.
6. The semiconductor device according to claim 5 , wherein
the TDC arrays comprise a plurality of digital counters formed in the second semiconductor layer, each configured to count output pulses from the region of a respective one of the SPADs.
7. The semiconductor device according to claim 5 , wherein:
the SPAD wafer further comprises a first dielectric interconnect layer comprising a first dielectric layer and a first metal layer embedded in the first dielectric layer;
the TDC wafer further comprises a second dielectric interconnect layer comprising a second dielectric layer and a second metal layer embedded in the second dielectric layer; and
the bonding is hybrid with the first dielectric layer facing the second dielectric layer and with the first metal layer facing the second metal layer.
8. The semiconductor device according to claim 1 , wherein the TDC arrays are arranged in a same manner as the SPAD arrays.
9. The semiconductor device according to claim 1 , wherein the peripheral logic circuits are so coupled to receive and store outputs from the TDC arrays.
10. The semiconductor device according to claim 1 , wherein the peripheral logic circuits include at least one of quenching circuits, reset circuits, signal detection circuits, readout circuits, control circuits and static random access memories.
11. The semiconductor device according to claim 10 , wherein the logic wafer comprises a third semiconductor layer containing the static random access memories, and wherein data from the TDC array is coupled and stored on the static random access memories.
12. The semiconductor device according to claim 1 , further comprising through silicon vias, which extend through the TDC wafer and contain a second interconnect layer electrically connecting the SPAD wafer to the logic wafer.
13. The semiconductor device according to claim 1 , a side of the SPAD wafer away from the TDC wafer has a first pad formed thereon, and a side of the logic wafer away from the TDC wafer has a second pad formed thereon, the first pad electrically connected to the second pad.
14. A semiconductor die, comprising:
a single-photon avalanche diode (SPAD) die formed thereon with a SPAD array;
a time to digital converter (TDC) die formed thereon with a TDC array; and
a logic die formed thereon with a peripheral logic circuit,
wherein the SPAD die, the TDC die and the logic die are bonded in the sequence set forth, and wherein the SPAD die, the TDC die and the logic die are sized so as to have a same area.
15. The semiconductor die according to claim 14 , wherein the SPAD die contains multiple SPADs and the TDC die contains multiple TDCs, and wherein a number of the SPADs on the SPAD die is equal to a number of the TDCs on the TDC die.
16. The semiconductor die according to claim 15 , wherein each SPAD on each SPAD die occupies an area the same as an area occupied by each TDC on each TDC die.
17. The semiconductor die according to claim 15 , wherein each SPAD on each SPAD die occupies an area different from an area occupied by each TDC on each TDC die.
18. The semiconductor die according to claim 14 , wherein the TDC array is arranged in a same manner as the SPAD array.