Transimpedance amplifier
A transimpedance amplifier (TIA) for converting an input current at an input node into an output voltage at an output node, the TIA comprising: a first amplifier stage having a first input coupled to the input node and a first output; a feedback path between the first output and the first input; a second amplifier stage in the feedback path having a second input, the second input coupled to the first output of the first amplifier stage; a feedback resistor in the feedback path coupled between an output of the second amplifier stage and first input of the first amplifier stage; and an output stage, comprising: a load resistor coupled between a reference voltage node and a T-coil, the T-coil comprising first and second inductors coupled in series at an inductor node, the T-coil coupled between the first output and the load resistor, the inductor node coupled to the output node of the TIA.
1. A transimpedance amplifier (TIA) for converting an input current at an input node into an output voltage at an output node, the TIA comprising:
a first amplifier stage having a first input coupled to the input node and a first output;
a feedback path between the first output and the first input;
a second amplifier stage in the feedback path having a second input, the second input coupled to the first output of the first amplifier stage;
a feedback resistor in the feedback path coupled between an output of the second amplifier stage and first input of the first amplifier stage; and
an output stage, comprising:
a load resistor coupled between a reference voltage node and a T-coil, the T-coil comprising first and second inductors coupled in series at an inductor node, the T-coil coupled between the first output and the load resistor, the inductor node coupled to the output node of the TIA.
2. The TIA of claim 1 , wherein the T-coil is a bridged T-coil, wherein the T-coil further comprises a bridge capacitor coupled between the first output and the load resistor.
3. The TIA of claim 1 , wherein the first reference voltage node is a supply voltage node.
4. The TIA of claim 1 , wherein the first amplifier stage comprises a transconductance amplifier.
5. The TIA of claim 1 , wherein the first amplifier stage comprises a common emitter amplifier comprising:
a first bipolar junction transistor (BJT), having:
a first base coupled to the first input of the first amplifier stage;
a first emitter coupled to a second reference voltage node; and
a first collector coupled to the first output of the first amplifier stage.
6. The TIA of claim 1 , wherein the first amplifier stage comprises a cascoded common emitter amplifier.
7. The TIA of claim 6 , wherein the cascoded common emitter amplifier comprises:
a common emitter BJT having a first base coupled to the first input, a first emitter coupled to a second reference voltage, and a first collector;
a cascode BJT having a second base coupled to a cascode bias voltage node, a second emitter coupled to the first collector, and a second collector coupled to the first output.
8. The TIA of claim 1 , wherein the first amplifier stage comprises:
a first BJT having a first base coupled to the first input, a collector coupled to the first output, and a first emitter;
a second BJT having a second base coupled to a second reference voltage node, a second collector coupled to a third reference voltage node, and a second emitter; and
a current source, the first and second emitters coupled to the current source.
9. The TIA of claim 1 , wherein the second amplifier stage has a voltage gain of approximately 1.
10. The TIA of claim 1 , wherein the second amplifier stage comprises an emitter follower amplifier comprising:
a second BJT, having:
a second base coupled to the first output of the first amplifier stage;
a second collector coupled to a third reference voltage node; and
a second emitter coupled to the feedback resistor.
11. The TIA of claim 1 , wherein the first amplifier stage comprises a common source amplifier.
12. The TIA of claim 11 , wherein the common source amplifier comprises a first CMOS device having:
a first gate coupled to the first input of the first amplifier stage;
a first source coupled to a second reference voltage node; and
a first drain coupled to the first output of the first amplifier.
13. The TIA of claim 1 , wherein the second amplifier stage comprises a source follower amplifier.
14. The TIA of claim 13 , wherein the source follower amplifier comprises a second CMOS device having:
a second gate coupled to the first output of the first amplifier stage;
a second source coupled to the feedback resistor; and
a second drain coupled to a second reference voltage node.
15. The TIA of claim 1 , further comprising a third amplifier stage coupled to the output node.
16. The TIA of claim 15 , wherein the third amplifier stage is a limiting amplifier or a variable gain amplifier (VGA).
17. The TIA of claim 1 , wherein the first amplifier stage comprises a transconductance amplifier coupled to the input node and configured to generate the input current.
18. An optical receiver comprising:
a photodiode for generating the input current; and
the TIA of claim 1 .
19. The optical receiver of claim 18 , wherein the photodiode is reverse biased.
20. An electronic device comprising the TIA of claim 1 .
21. The electronic device of claim 20 , wherein the electronic device is one of an optical receiver, a Geiger-Muller tube, a photo multiplier tube or an accelerometer.