Trap sub-portions of computer-readable instructions and related systems, methods, and apparatuses

1. An apparatus, comprising:

a processing core including a program counter to cycle through addresses; and

a data storage device including computer-readable instructions stored thereon, the computer-readable instructions including sub-portions of the computer-readable instructions to instruct the processing core to execute subroutines, each sub-portion of the computer-readable instructions corresponding to one of the subroutines, locations of the sub-portions of the computer-readable instructions within the data storage device associated with the addresses, the sub-portions including:

a first sub-portion at a first location within the data storage device indicated by a first address; and

first trap sub-portions at first trap locations within the data storage device, the first trap sub-portions indicated by respective first trap addresses, the first trap addresses different from the first address by only a single bit, the first trap sub-portions to instruct the processing core to execute respective first trap subroutines to jump to one of the first address or to themselves.

2. The apparatus of claim 1 , wherein the first address is a consecutive series of zeros.

3. The apparatus of claim 1 , wherein the first address comprises a plurality of bits, each of the first trap addresses differing from the first address by a single respective bit.

4. The apparatus of claim 1 , wherein the sub-portions include:

a second sub-portion at a second location within the data storage device indicated by a second address, the second address a ones' complement of the first address, the first sub-portion to instruct the processing core to execute a first subroutine to jump to the second address; and

second trap sub-portions at second trap locations within the data storage device, the second trap locations indicated by second trap addresses, the second trap addresses different from the second address by only a single bit, the second trap sub-portions to instruct the processing core to execute second trap subroutines to jump to the second address or to themselves.

5. The apparatus of claim 4 , wherein one of the first address and the second address is a consecutive series of zeros and one of the first address and the second address is a consecutive series of ones.

6. The apparatus of claim 1 , wherein the sub-portions include:

a second sub-portion at a second location within the data storage device indicated by a second address, the second address a ones' complement of the first address, the first sub-portion to instruct the processing core to execute a first subroutine to jump to the second address; and

second trap sub-portions at second trap locations within the data storage device, the second trap locations indicated by second trap addresses, the second trap addresses different from the second address by only a single bit, the second trap sub-portions to instruct the processing core to execute second trap subroutines to jump to the second address, to themselves, or to the first address.

7. The apparatus of claim 6 , comprising an address bus electrically connecting the program counter to the data storage device, wherein the second trap sub-portions prevent a jump to an unknown address in the event of a single stuck-at low bit fault at one or more of the address bus or the program counter.

8. The apparatus of claim 1 , comprising a watchdog timer to detect a fault of the program counter or of an address bus electrically connecting the program counter to the data storage device during run-time, the watchdog timer to initiate a reset operation responsive to detecting the fault of the program counter during run-time.

9. The apparatus of claim 8 , wherein the watchdog timer is implemented independently from the subroutines.

10. The apparatus of claim 8 , the watchdog timer to initiate the reset operation independently from the processing core.

11. The apparatus of claim 8 , wherein the watchdog timer is implemented in hardware separate from the processing core.

12. The apparatus of claim 1 , comprising an address bus electrically connecting the program counter to the data storage device, wherein the first trap sub-portions prevent a jump to an unknown address in the event of a single stuck-at high bit fault at one or more of the address bus or the program counter.

13. A system, comprising:

a processing circuit, the processing circuit comprising:

a processing core including a program counter to cycle through addresses;

a data storage device including computer-readable instructions stored thereon, the computer-readable instructions including sub-portions of the computer-readable instructions, the sub-portions to instruct the processing core to execute subroutines, the sub-portions including:

a first sub-portion at a first location within the data storage device indicated by a first address of the addresses;

first trap sub-portions at first trap locations within the data storage device, the first trap locations indicated by respective first trap addresses of the addresses, the first trap addresses different from the first address by only a single respective bit, the first trap sub-portions to instruct the processing core to execute first trap subroutines to jump to the first address or back to themselves;

a second sub-portion at a second location within the data storage device indicated by a second address of the addresses, the second address a ones' complement of the first address, the first sub-portion to instruct the processing core to execute a first subroutine to jump to the second address; and

second trap sub-portions at second trap locations within the data storage device, the second trap locations indicated by respective second trap addresses of the addresses, the second trap addresses different from the second address by only a single respective bit, the second trap sub-portions to instruct the processing core to execute second trap subroutines to jump to the second address, to themselves, or to the first address.

14. The system of claim 13 , wherein numbers of the first trap sub-portions and the second trap sub-portions are each equal to a number of bits of the addresses.

15. A method of operating a processing circuit, the method comprising:

initiating cycling of addresses in a program counter with a first address corresponding to a first sub-portion of computer-readable instructions stored by a data storage device at a first location;

executing, responsive to the first address in the program counter and a first type of stuck-at fault of the program counter or of an address bus, a first trap subroutine corresponding to a first trap sub-portion of the computer-readable instructions to jump to the first address or to itself;

executing, responsive to the first address in the program counter and the address bus being free of the first type of stuck-at fault, a first sub-routine corresponding to the first sub-portion of the computer-readable instructions to jump to a second address corresponding to a second sub-portion of the computer-readable instructions at a second location of the data storage device; and

executing, responsive to the second address in the program counter and a second type of stuck-at fault of the program counter or of the address bus, a second trap subroutine corresponding to a second trap sub-portion of the computer-readable instructions to jump to the second address, to the first address, or to itself.

16. The method of claim 15 , comprising executing, responsive to the second address in the program counter or of the address bus being free of the second type of stuck-at fault, a second subroutine corresponding to a second sub-portion of the computer-readable instructions to jump to a start of application address corresponding to an application sub-portion of the computer-readable instructions and an application subroutine.

17. The method of claim 15 , comprising:

detecting, during a run-time of the processing circuit, a fault in operation of the processing circuit; and

resetting operation of the processing circuit responsive to the detected fault.

18. The method of claim 17 , wherein detecting the fault comprises detecting a stuck-at fault of the program counter or of the address bus by one of a watchdog timer and a diagnostic test.

19. The method of claim 15 , wherein the first type of stuck-at fault is a stuck-at high fault and the second type of stuck-at fault is a stuck-at low fault.

20. The method of claim 15 , wherein initiating the cycling of the addresses in the program counter with the first address comprises initiating the cycling of the addresses in the program counter with the first address including a consecutive series of all zeros.